Computation and Communication Optimization in Many-Core Heterogeneous Server-on-Chip

• Main Author: Reza, Md Farhadur
• Language: EN
• Published: University of Louisiana at Lafayette 2018
• Subjects: Computer engineering|Computer science
• Online Access: http://pqdtopen.proquest.com/#viewpdf?dispub=10687409

<p> To make full use of parallelism of many cores in network-on-chip (NoC) based server-on-chip, this dissertation addresses the problem of computation and communication optimization during task-resource co-allocation of large-scale applications onto heterogeneous NoCs. Both static and dynamic task mapping and resource configuration have been performed while making the solution aware of power, thermal, dark/dim silicon, and capacity issues of chip. Our objectives are to minimize energy consumption and hotspots for improving NoC performance in terms of latency and throughput while meeting the above-mentioned chip constraints. Task-resource allocation and configuration problems have been formulated using linear programming (LP) optimization for optimal solutions. Due to high time complexity of LP solutions, fast heuristic approaches are proposed to get the near-optimal mapping and configuration solutions in a finite time for many-core systems. </p><p> &bull; We first present the hotspots minimization problems and solutions in NoC based many-core server-on-chip considering both computation and communication demands of the applications while meeting the chip constraints in terms of chip area budget, computational capacity of nodes, and communication capacity of links. </p><p> &bull; We then address power and thermal limitations in dark silicon era by proposing run-time resource management strategy and mapping for minimization of both hotspots and overall chip energy in many-core NoC. </p><p> &bull; We then present the power-thermal aware load-balanced mapping in heterogeneous CPU-GPU systems in many-core NoC. Distributed resource management strategy in CPU-GPU system using CPUs for system management and latency-sensitive tasks and GPUs for throughput-intensive tasks has been proposed. </p><p> &bull; We propose a neural network model to dynamically monitor, predict, and configure NoC resources. This work applies local and global neural networks classifiers for configuring NoC based on demands of applications and chip constraints. </p><p> &bull; Due to the integration of many-cores in a single chip, we propose express channels for improving NoC performance in terms of latency and throughput. We also propose mapping methodologies for efficient task-resource co-allocation in express channel enabled many-core NoC.</p><p>