Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic

Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic

Bibliographic Details
Main Author:	Yelamarthi, Kumar
Language:	English
Published:	Wright State University / OhioLINK 2008
Subjects:	Electrical Engineering process variation adders transistor sizing mixed-static-dynamic timing optimization
Online Access:	http://rave.ohiolink.edu/etdc/view?acc_num=wright1213880942

Similar Items

From static ternary adders to high-performance race-free dynamic ones
by: Shirin Rezaie, et al.
Published: (2015-12-01)

Low-Power Adder Design for Nano-Scale CMOS
by: S. R. Talebiyan, et al.
Published: (2009-09-01)

Two novel low-power and high-speed dynamic carbon nanotube full-adder cells
by: Eshghi Mohammad, et al.
Published: (2011-01-01)

DESIGN AND SOFTWARE CHARACTERIZATION OF FINFET BASED FULL ADDERS
by: Raju Hajare, et al.
Published: (2019-01-01)

Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL
by: Khaled Alhaj Ali, et al.
Published: (2021-04-01)

Hybrid memristor-CMOS implementation of logic gates design using LTSpice
by: Al-Junid, S.A.M, et al.
Published: (2021)

Optimal performance of 16-bit acyclic adders of binary codes
by: Mykhailo Solomko, et al.
Published: (2019-06-01)

Design, implementation and performance comparison of multiplier topologies in power-delay space
by: Mansi Jhamb, et al.
Published: (2016-03-01)

Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations
by: Marco Lanuzza, et al.
Published: (2011-04-01)

HIGH PERFORMANCE WALLACE TREE MULTIPLIER USING IMPROVED ADDER
by: Meenali Janveja, et al.
Published: (2017-04-01)

Fast Mux-based Adder with Low Delay and Low PDP
by: H. Tavakolaee, et al.
Published: (2019-07-01)

FARHAD: a Fault-Tolerant Power-Aware Hybrid Adder for High-Performance Processor
by: Hajkazemi, Mohammad Hossein
Published: (2013)

A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization
by: Muhammad Ali Akbar, et al.
Published: (2021-07-01)

Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis
by: Mehedi Hasan, et al.
Published: (2021-05-01)

Design and Simulation of a Nanoscale Threshold-Logic Multiplier
by: Mawahib Hussein Sulieman, et al.
Published: (2019-05-01)

Mental, Physical and Mixed Practice Effects on Elderly Static and Dynamic Balance
by: Mohammad Ali Aslankhani, et al.
Published: (2008-10-01)

Design methodologies for robust low-power digital systems under static and dynamic variations
by: Chae, Kwanyeob
Published: (2014)

Synthesis of 64 bit Energy Efficient and Reconfigurable Adder
by: Dara, chandra babu
Published: (2009)

Implementation of Pipelined Bit-parallel Adders
by: Wei, Lan
Published: (2003)

Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications
by: T. Suguna, et al.
Published: (2020-04-01)

Compact variation-aware standard cells for statistical static timing analysis
by: Aftabjahani, Seyed-Abdollah
Published: (2011)

The impact of brain gym on static and dynamic balance in elderly
by: Mohsen Amiri, et al.
Published: (2016-02-01)

The comparative characteristic of influence of unitary static and dynamic efforts with own weight of a body on parameters variational pulse rate at the boys aged 10 – 11 years
by: E.M. Proskurov
Published: (2013-02-01)

Pipelined Two-Operand Modular Adders
by: M. Czyzak, et al.
Published: (2015-04-01)

Microfluidic time‐lapse analysis and reevaluation of the Bacillus subtilis cell cycle
by: Seoungjun Lee, et al.
Published: (2019-10-01)

The Acute Effects of Static and Dynamic Stretching Exercises on Dynamic Balance Performance
by: Nevzad Denerel, et al.
Published: (2019-02-01)

A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells
by: Arezoo Dabaghi Zarandi, et al.
Published: (2020-01-01)

Static and dynamic balance in young athletes
by: Leonardo Ricotti
Published: (2011-12-01)

Static and dynamic balance in young athletes
by: LEONARDO RICOTTI
Published: (2011-12-01)

The Effects of Backpack Weight on the Static and Dynamic Balances of Female Students
by: Saeid Bahiraei, et al.
Published: (2015-10-01)

EXPERIMENTAL STUDIES ON MULTI-OPERAND ADDERS
by: S. D. Thabah, et al.
Published: (2017-06-01)

CNTFET BASED NOVEL 14T ADDER CELL FOR LOW POWER COMPUTATION
by: Balaji Ramakrishna S, et al.
Published: (2017-10-01)

CNTFET BASED NOVEL 14T ADDER CELL FOR LOW POWER COMPUTATION
by: Balaji Ramakrishna S, et al.
Published: (2017-10-01)

64 x 64 Bit Multiplier Using Pass Logic
by: Thankachan, Shibi
Published: (2006)

Kajian Pengunaan Static Mixing Reactor Pada Proses Produksi Biodiesel Secara Katalitik Dengan Sistem Continue
by: Christian Soolany, et al.
Published: (2015-09-01)

A Constant Delay Logic Style - An Alternative Way of Logic Design
by: Chuang, Pierce I Jen
Published: (2010)

A Constant Delay Logic Style - An Alternative Way of Logic Design
by: Chuang, Pierce I Jen
Published: (2010)

An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic
by: Shoba Mohan, et al.
Published: (2017-06-01)

Comparison of the Effect of Insole with Different Widgets on Static and Dynamic Balance
by: Ali Yalfani, et al.
Published: (2020-06-01)

Static and Dynamic Balance of the Healthy Elderly Men at Different Times of the Day
by: Saeed Ghaeeni, et al.
Published: (2015-10-01)

Cannot write session to /tmp/vufind_sessions/sess_nnaocrlcsma1ptrfgfrtvtkmth