Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic

Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic

Bibliographic Details
Main Author: Yelamarthi, Kumar
Language:English
Published: Wright State University / OhioLINK 2008
Subjects:
Electrical Engineering
process variation
adders
transistor sizing
mixed-static-dynamic
timing optimization
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=wright1213880942
id ndltd-OhioLink-oai-etd.ohiolink.edu-wright1213880942
record_format oai_dc
spelling ndltd-OhioLink-oai-etd.ohiolink.edu-wright12138809422021-08-03T06:16:44Z Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic Yelamarthi, Kumar Electrical Engineering process variation adders transistor sizing mixed-static-dynamic timing optimization <p>The semiconductor technology has been advancing rapidly over the past decade to result in the design of several innovative applications. This advancement of technology with the shrinking device has allowed for placement of billions of transistor on a single microprocessor chip. On the other hand, this shrinking device sizes has presented the design engineers with two major challenges: timing optimization at multiple giga-hertz frequencies, and reducing the daunting effects of semiconductor process variations. Failure to account for these process variations often results in loss of design productivity by one generation, and might even result in design failure.</p><p>This research presents two timing optimization algorithms while accounting for process variations. The process variation-aware Load Balance of Multiple Paths (LBMP) algorithm is designed for timing optimization of dynamic CMOS circuits. Implemented on several dynamic CMOS circuits, the LBMP algorithm has demonstrated an average reduction in delay, uncertainty, and sensitivity from process variations by 48%, 57% and 14% respectively. The process variation-aware Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS circuits partitions a design based on critical paths, chooses effective circuit style, and performs switch level timing optimization using the LBMP algorithm. Verified through implementation on several standard benchmark circuits, the POINT optimization flow has demonstrated an average reduction in delay and uncertainty from process variations by 17% and 13% over state-of-the-art commercial optimization tools.</p> 2008-06-23 English text Wright State University / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=wright1213880942 http://rave.ohiolink.edu/etdc/view?acc_num=wright1213880942 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection NDLTD
language English
sources NDLTD
topic Electrical Engineering
process variation
adders
transistor sizing
mixed-static-dynamic
timing optimization
spellingShingle Electrical Engineering
process variation
adders
transistor sizing
mixed-static-dynamic
timing optimization
Yelamarthi, Kumar
Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic
author Yelamarthi, Kumar
author_facet Yelamarthi, Kumar
author_sort Yelamarthi, Kumar
title Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic
title_short Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic
title_full Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic
title_fullStr Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic
title_full_unstemmed Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic
title_sort process variation-aware timing optimization with load balance of multiple paths in dynamic and mixed-static-dynamic cmos logic
publisher Wright State University / OhioLINK
publishDate 2008
url http://rave.ohiolink.edu/etdc/view?acc_num=wright1213880942
work_keys_str_mv AT yelamarthikumar processvariationawaretimingoptimizationwithloadbalanceofmultiplepathsindynamicandmixedstaticdynamiccmoslogic
_version_ 1719433961605693440

Similar Items