Simulation and Design of InAs Nanowire Transistors Using Ballistic Transport

Simulation and Design of InAs Nanowire Transistors Using Ballistic Transport

Bibliographic Details
Main Author: Myers Riggs, Rhonda Renee
Language:English
Published: University of Cincinnati / OhioLINK 2005
Subjects:
Nanowire
Device modeling
Simulation
Indium Arsenide
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=ucin1192729325
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spelling ndltd-OhioLink-oai-etd.ohiolink.edu-ucin11927293252021-08-03T06:12:09Z Simulation and Design of InAs Nanowire Transistors Using Ballistic Transport Myers Riggs, Rhonda Renee Nanowire Device modeling Simulation Indium Arsenide The purpose of this thesis is to describe the modeling of the performance of InAs nanowire MOSFETs and to study their performance as parameter of the transistor’s structure (e.g., diameter, gate dielectric thickness, and gate dielectric constant) were changed. This study was performed using the FETToy (www.nanohub.org) modeling software [35, 36] developed at Purdue University. FETToy is composed of several Matlab scripts and is used to simulate ballistic transport in the calculation of the current-voltage (I-V) characteristics for nanoscale double gate silicon MOSFETs. By modifying the semiconductor’s effective mass, the program can be used to model semiconductors other than silicon. This thesis presents in Chapter 2 the initial modeling results for an InAs nanowire MOSFET in comparison with the published experimental results for a 80 nm diameter nanowire MOSFET as reported by Bryllert et al.’s (Sweden) group [23, 24]. Comparisons were made of the simulation results to the experimental results for the transistor’s drain current versus gate voltage to extract the threshold voltage, the transistor’s output characteristics (drain current versus drain bias for various gate voltages), the log of the drain current versus the gate voltage (subthreshold plot), and the transconductance versus gate voltage for a drain voltage in the saturation region. Chapter 3 describes the results obtained from varying the transistor’s structure from the initial one used in Chapter 2 to compare with the published experimental results. This includes the effects on transistor performance of variation in the nanowire diameter, gate dielectric thickness, and gate dielectric constant. This chapter also pursues the optimization of the device’s performance by altering the device’s structure. We conclude this thesis by summarizing the work presented here and offering suggestions for future work. 2005 English text University of Cincinnati / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=ucin1192729325 http://rave.ohiolink.edu/etdc/view?acc_num=ucin1192729325 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection NDLTD
language English
sources NDLTD
topic Nanowire
Device modeling
Simulation
Indium Arsenide
spellingShingle Nanowire
Device modeling
Simulation
Indium Arsenide
Myers Riggs, Rhonda Renee
Simulation and Design of InAs Nanowire Transistors Using Ballistic Transport
author Myers Riggs, Rhonda Renee
author_facet Myers Riggs, Rhonda Renee
author_sort Myers Riggs, Rhonda Renee
title Simulation and Design of InAs Nanowire Transistors Using Ballistic Transport
title_short Simulation and Design of InAs Nanowire Transistors Using Ballistic Transport
title_full Simulation and Design of InAs Nanowire Transistors Using Ballistic Transport
title_fullStr Simulation and Design of InAs Nanowire Transistors Using Ballistic Transport
title_full_unstemmed Simulation and Design of InAs Nanowire Transistors Using Ballistic Transport
title_sort simulation and design of inas nanowire transistors using ballistic transport
publisher University of Cincinnati / OhioLINK
publishDate 2005
url http://rave.ohiolink.edu/etdc/view?acc_num=ucin1192729325
work_keys_str_mv AT myersriggsrhondarenee simulationanddesignofinasnanowiretransistorsusingballistictransport
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