BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS

BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS

Bibliographic Details
Main Author: PATEL, VIPUL J.
Language:English
Published: University of Cincinnati / OhioLINK 2006
Subjects:
Delta-Sigma
Sigma-Delta
Top-Down
Bottom-Up
Modulator
Methodology
Analog
RF
Digital
Synthesis
Analog Synthesis
Layout
Parasitics
Behavioral Modeling
Layout-Aware
MATLAB
Simulink
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065
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spelling ndltd-OhioLink-oai-etd.ohiolink.edu-ucin11474730652021-08-03T06:10:56Z BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS PATEL, VIPUL J. Delta-Sigma Sigma-Delta Top-Down Bottom-Up Modulator Methodology Analog RF Digital Synthesis Analog Synthesis Layout Parasitics Behavioral Modeling Layout-Aware MATLAB Simulink For the past few decades, research and design of CAD tools have focused on developing a set of tools that will guarantee designers first-pass fabrication success. There have been many variations of digital design “suites” that make this claim. With the increase in integrated circuit complexity and the drive for systems-on-a-chip (SoC), companies and universities are now focusing their efforts on creating design tools addressing the analog and RF domains. System-level design is one of the most important and challenging elements in the mixed-signal design process. Currently, many system designs are approached from a bottom-up perspective where components are designed individually and then assembled at the system-level. Concepts such as analog and digital interfacing, defining component specifications, and system verification are typically lacking or are addressed too late. Rapid modeling and component-level trade-offs are important in the design of systems. Many of these integration issues can be addressed early in the design phase by having the capability to predict and model component-level effects. In order to address these issues of system design and synthesis, four primary tools have been developed. These tools include (1) a continuous-time delta-sigma system modeler and designer, (2) a circuit sizer, (3) a performance analysis system, and (4) a parameterized module layout generator. Various analog synthesis flows have been developed using these tools. The first goal of this thesis is to provide the design community with a behavioral environment that will model and aid in the creation of continuous-time single-loop single-bit baseband delta-sigma analog-to-digital modulators using MATLAB and Simulink. The second goal is to use the designs from the delta-sigma toolbox to produce component-level specifications derived from system-level requirements. In this thesis, the developed tools were used in a synthesis loop to design, implement, and verify two continuous-time delta-sigma modulators and their respective components. A third order modulator was designed with 1 MHz instantaneous bandwidth and a sampling rate of 64 MSps using the top-down design methodology. The modulator performed with an SNR of 60 dB and ENOB of 9.7 bits. A fourth order modulator with a sample rate of 50 MSps was designed with a bandwidth of 390 kHz, and the bottom-up design methodology was used. This design performed with an SNR of 74.2 dB and ENOB of 12.0 bits. 2006-10-02 English text University of Cincinnati / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065 http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection NDLTD
language English
sources NDLTD
topic Delta-Sigma
Sigma-Delta
Top-Down
Bottom-Up
Modulator
Methodology
Analog
RF
Digital
Synthesis
Analog Synthesis
Layout
Parasitics
Behavioral Modeling
Layout-Aware
MATLAB
Simulink
spellingShingle Delta-Sigma
Sigma-Delta
Top-Down
Bottom-Up
Modulator
Methodology
Analog
RF
Digital
Synthesis
Analog Synthesis
Layout
Parasitics
Behavioral Modeling
Layout-Aware
MATLAB
Simulink
PATEL, VIPUL J.
BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS
author PATEL, VIPUL J.
author_facet PATEL, VIPUL J.
author_sort PATEL, VIPUL J.
title BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS
title_short BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS
title_full BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS
title_fullStr BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS
title_full_unstemmed BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS
title_sort behavioral simulation and synthesis environment for continuous-time single-loop single-bit baseband delta-sigma analog-to-digital modulators
publisher University of Cincinnati / OhioLINK
publishDate 2006
url http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065
work_keys_str_mv AT patelvipulj behavioralsimulationandsynthesisenvironmentforcontinuoustimesingleloopsinglebitbasebanddeltasigmaanalogtodigitalmodulators
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