LOW POWER FPGA DESIGN TECHNIQUES FOR EMBEDDED SYSTEMS

LOW POWER FPGA DESIGN TECHNIQUES FOR EMBEDDED SYSTEMS

Bibliographic Details
Main Author: TIWARI, ANURAG
Language:English
Published: University of Cincinnati / OhioLINK 2005
Subjects:
Low Power
FPGA
FSM
Finite State Machine
Technology mapping
Synthesis
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109352677
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spelling ndltd-OhioLink-oai-etd.ohiolink.edu-ucin11093526772021-08-03T06:10:13Z LOW POWER FPGA DESIGN TECHNIQUES FOR EMBEDDED SYSTEMS TIWARI, ANURAG Low Power FPGA FSM Finite State Machine Technology mapping Synthesis In the past few decades with advancement in VLSI technology, FPGA chip density has increased and FPGA devices now provide a large number of smaller feature size transistors and can support higher clock speeds. While this advancement is beneficial for implementing larger and faster designs within a single chip, it also leads to increased power consumption. With the remarkable growth of FPGA based battery-powered systems, such as personal computing devices, wireless equipment, space-borne systems, and consumer electronics, low power FPGA design is of increased importance. In this thesis, I investigate various FPGA design techniques to minimize dynamic power consumed by an FPGA design. The objective of this research is to minimize the power drawn by a design without altering its functionality and with minimal or no impact on its timing. The work focuses on the implementation of control logic within a design. Reduction of power consumption of an FPGA design is attempted at the following design stages: high-level synthesis, mapping and placement and routing stage. In addition, power consumed by fault tolerant finite state machines in FPGAs is also addressed, and it has been shown that power consumed by the proposed alternate design is significantly lower than a traditional fault tolerant design. The central idea behind all the design techniques proposed is to reduce the switching activity on the power hungry programmable interconnection network. Power consumed by the clock network which also consumes a considerable amount of power is also reduced by selective clocking of finite state machines. The techniques and algorithms presented in this thesis can be easily automated and can be incorporated in an existing FPGA design flow. 2005-05-31 English text University of Cincinnati / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109352677 http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109352677 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection NDLTD
language English
sources NDLTD
topic Low Power
FPGA
FSM
Finite State Machine
Technology mapping
Synthesis
spellingShingle Low Power
FPGA
FSM
Finite State Machine
Technology mapping
Synthesis
TIWARI, ANURAG
LOW POWER FPGA DESIGN TECHNIQUES FOR EMBEDDED SYSTEMS
author TIWARI, ANURAG
author_facet TIWARI, ANURAG
author_sort TIWARI, ANURAG
title LOW POWER FPGA DESIGN TECHNIQUES FOR EMBEDDED SYSTEMS
title_short LOW POWER FPGA DESIGN TECHNIQUES FOR EMBEDDED SYSTEMS
title_full LOW POWER FPGA DESIGN TECHNIQUES FOR EMBEDDED SYSTEMS
title_fullStr LOW POWER FPGA DESIGN TECHNIQUES FOR EMBEDDED SYSTEMS
title_full_unstemmed LOW POWER FPGA DESIGN TECHNIQUES FOR EMBEDDED SYSTEMS
title_sort low power fpga design techniques for embedded systems
publisher University of Cincinnati / OhioLINK
publishDate 2005
url http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109352677
work_keys_str_mv AT tiwarianurag lowpowerfpgadesigntechniquesforembeddedsystems
_version_ 1719432065710030848

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