IMPLEMENTATION OF A DYNAMICALLY RECONFIGURABLE ASYNCHRONOUS PROGRAMMABLE LOGIC (DRAPL) ARCHITECTURE

IMPLEMENTATION OF A DYNAMICALLY RECONFIGURABLE ASYNCHRONOUS PROGRAMMABLE LOGIC (DRAPL) ARCHITECTURE

Bibliographic Details
Main Author:	RAJAGOPALAN, JAYANTHI
Language:	English
Published:	University of Cincinnati / OhioLINK 2004
Subjects:	Asynchronous FPGA Self-timing Handshaking communication Timing Cell Timing Region Programmable Logic
Online Access:	http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100886361

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