IMPROVING SIMULATION TIME USING MULTITHREADING IN FREQUENCY EXTENDED VHDL-AMS
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2003
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ndltd-OhioLink-oai-etd.ohiolink.edu-ucin10456749382021-08-03T06:09:02Z IMPROVING SIMULATION TIME USING MULTITHREADING IN FREQUENCY EXTENDED VHDL-AMS SRINIVASAN, RAGHURAM multithreading frequency domain VHDL-AMS circuit simulation computer aided design VHDL-AMS simulators are becoming increasingly popular as the presence of analog components in a design is becoming more common. Much attention has been placed on optimizing the simulators since they take very large amounts of time to analyze a model as compared to digital circuit simulators. In addition, as the capability of the simulators increase, the optimizations become more important as the number of parameters controlling simulation is higher. This thesis presents a survey of possible approaches for optimizing VHDL-AMS simulators with Multithreaded Architectures. The focus, however, is applying Multithreaded Architectures to the frequency domain kernel. The internals of the existing frequency domain kernel are discussed at length. Additions to the VHDL-AMS language are proposed for frequency domain simulation. Protocols for time and frequency domain simulation are presented with examples. Multithreaded Architectures for optimizing the frequency domain kernel in VHDL-AMS simulators are presented. The output based approach utilizes the inherent delays in computation and output that are present in the simulation kernel while the frequency bands approach relies on the fact that linear solvers are not iterative in nature. The problems faced during splitting the simulation into threads are described along with indications to possible race hazards. Finally, conclusions drawn from this work are presented. Pointers for future work in terms of frequency domain simulation and multithreading the simulation routines are provided. 2003-04-17 English text University of Cincinnati / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=ucin1045674938 http://rave.ohiolink.edu/etdc/view?acc_num=ucin1045674938 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws. |
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language |
English |
sources |
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topic |
multithreading frequency domain VHDL-AMS circuit simulation computer aided design |
spellingShingle |
multithreading frequency domain VHDL-AMS circuit simulation computer aided design SRINIVASAN, RAGHURAM IMPROVING SIMULATION TIME USING MULTITHREADING IN FREQUENCY EXTENDED VHDL-AMS |
author |
SRINIVASAN, RAGHURAM |
author_facet |
SRINIVASAN, RAGHURAM |
author_sort |
SRINIVASAN, RAGHURAM |
title |
IMPROVING SIMULATION TIME USING MULTITHREADING IN FREQUENCY EXTENDED VHDL-AMS |
title_short |
IMPROVING SIMULATION TIME USING MULTITHREADING IN FREQUENCY EXTENDED VHDL-AMS |
title_full |
IMPROVING SIMULATION TIME USING MULTITHREADING IN FREQUENCY EXTENDED VHDL-AMS |
title_fullStr |
IMPROVING SIMULATION TIME USING MULTITHREADING IN FREQUENCY EXTENDED VHDL-AMS |
title_full_unstemmed |
IMPROVING SIMULATION TIME USING MULTITHREADING IN FREQUENCY EXTENDED VHDL-AMS |
title_sort |
improving simulation time using multithreading in frequency extended vhdl-ams |
publisher |
University of Cincinnati / OhioLINK |
publishDate |
2003 |
url |
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1045674938 |
work_keys_str_mv |
AT srinivasanraghuram improvingsimulationtimeusingmultithreadinginfrequencyextendedvhdlams |
_version_ |
1719431719022493696 |