Hardware Evaluation of the Round 2 NIST Lightweight Cryptography Candidates using High Level Synthesis

Bibliographic Details
Main Author:	Manifold, Megan
Language:	English
Published:	The Ohio State University / OhioLINK 2020
Subjects:	Electrical Engineering
Online Access:	http://rave.ohiolink.edu/etdc/view?acc_num=osu160676214356098

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spelling	ndltd-OhioLink-oai-etd.ohiolink.edu-osu1606762143560982021-10-15T05:10:51Z Hardware Evaluation of the Round 2 NIST Lightweight Cryptography Candidates using High Level Synthesis Manifold, Megan Electrical Engineering As technology advances the number of resource-constrained smart devices in use is increasing dramatically. As more sensitive applications come to rely upon these smart devices, mechanisms must be in place to protect them and the data they are handling. The National Institute of Standards and Technology (NIST) Lightweight Cryptography (LWC) project looks to fill this need by identifying a standard for lightweight cryptography to be used in resource constrained devices. Part of the project is an evaluation of potential algorithms over multiple rounds of review and analysis. The list started initially with 57 algorithms and is now reduced to 32. Due to time and resource constraints it is challenging to efficiently and uniformly create hardware implementations of each individual algorithm for comparison. In this work we propose using High Level Synthesis (HLS) as an implementation technology to fairly compare the candidate algorithms in hardware. HLS takes an algorithmic description written in a software coding language such as C, C++ or Python and performs behavioral synthesis to generate a register transfer level (RTL) description written in Verilog or VHDL. By automating the hardware design phase, HLS quickly generates hardware implementations. Additionally, HLS provides a fair platform for evaluation because it removes the variability introduced by individual hardware designers. This work provides preliminary hardware performance metrics for the NIST LWC candidate algorithms and provides an analysis on the feasibility of using a HLS design flow to accelerate encryption hardware design. 2020 English text The Ohio State University / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=osu160676214356098 http://rave.ohiolink.edu/etdc/view?acc_num=osu160676214356098 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection	NDLTD
language	English
sources	NDLTD
topic	Electrical Engineering
spellingShingle	Electrical Engineering Manifold, Megan Hardware Evaluation of the Round 2 NIST Lightweight Cryptography Candidates using High Level Synthesis
author	Manifold, Megan
author_facet	Manifold, Megan
author_sort	Manifold, Megan
title	Hardware Evaluation of the Round 2 NIST Lightweight Cryptography Candidates using High Level Synthesis
title_short	Hardware Evaluation of the Round 2 NIST Lightweight Cryptography Candidates using High Level Synthesis
title_full	Hardware Evaluation of the Round 2 NIST Lightweight Cryptography Candidates using High Level Synthesis
title_fullStr	Hardware Evaluation of the Round 2 NIST Lightweight Cryptography Candidates using High Level Synthesis
title_full_unstemmed	Hardware Evaluation of the Round 2 NIST Lightweight Cryptography Candidates using High Level Synthesis
title_sort	hardware evaluation of the round 2 nist lightweight cryptography candidates using high level synthesis
publisher	The Ohio State University / OhioLINK
publishDate	2020
url	http://rave.ohiolink.edu/etdc/view?acc_num=osu160676214356098
work_keys_str_mv	AT manifoldmegan hardwareevaluationoftheround2nistlightweightcryptographycandidatesusinghighlevelsynthesis
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Hardware Evaluation of the Round 2 NIST Lightweight Cryptography Candidates using High Level Synthesis

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