Dynamic Bandwidth and Laser Scaling for CPU-GPU Heterogenous Network-on-Chip Architectures
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Ohio University / OhioLINK
2017
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| Online Access: | http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1500992706350957 |
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ndltd-OhioLink-oai-etd.ohiolink.edu-ohiou15009927063509572021-08-03T07:03:35Z Dynamic Bandwidth and Laser Scaling for CPU-GPU Heterogenous Network-on-Chip Architectures Van Winkle, Scott E. Computer Engineering Electrical Engineering CPU GPU Heterogeneous Network on Chip Photonic Machine Learning Dynamic bandwidth scaling Dynamic power scaling As the relentless quest for higher throughput and lower energy cost continues in heterogenous multicores, there is a strong demand for energy-efficient and high-performance Network-on-Chip (NoC) architectures. Heterogenous architectures that can simultaneously utilize both the serialized nature of the CPU as well as the thread level parallelism of the GPU are gaining traction in the industry. A critical issue with heterogenous architectures is finding an optimal way to utilize the shared resources such as the last level cache (LLC) and NoC without hindering the performance of either the CPU or the GPU core. Photonic interconnects are a disruptive technology solution that have the potential to increase the bandwidth, reduce latency, and improve energy-efficiency over traditional metallic interconnects. In this thesis, we propose a CPU-GPU heterogenous architecture called SHARP (Shared Heterogenous Architecture with Reconfigurable Photonic Network-on-Chip) that combines CPU and GPU cores around the same router. SHARP architecture is designed as a Single-Writer Multiple-Reader (SWMR) crossbar with reservation-assist to connect CPU/GPU cores. The architecture consists of 32 CPU cores and 64 GPU computational units. As network traffic exhibits temporal and spatial fluctuations due to application behavior, SHARP can dynamically reallocate bandwidth and thereby adapt to application demands. In this thesis, we propose to dynamically reallocate bandwidth and reduce power consumption by evaluating buffer utilization. While buffer utilization is a reactive technique that deals with fluctuations in application demands, we also propose a proactive technique wherein we use machine learning (ML) to optimize the bandwidth and power consumption. In ML, instead of predicting the buffer utilization, we predict the number of packets that will be generated by the heterogenous cluster. Simulation results where evaluated using PARSEC 2.1 and SPLASH2 benchmark suits for the CPU and OpenCL SDK benchmark suite for the GPU. Our simulation results demonstrate a 34% performance (throughput) improvement over a baseline electrical CMESH while consuming 25% less energy per bit when dynamically reallocating bandwidth. Further simulation results have also shown 6.9% to 14.9% performance improvement over other flavors of the proposed SHARP architecture without dynamic bandwidth allocation. When dynamically scaling laser power, the laser power scaling without ML demonstrates an 8.2% throughput loss with a 60.5% laser power improvement of a high laser power baseline when the reservation window is set to 25 cycles. With a reservation window size of 2000 cycles, the laser power scaling with ML has a negligible throughput loss when compared to the high laser power baseline with a 42% laser power savings. With a reservation window size of 500 cycles, the laser power scaling with ML demonstrates a 14.6% throughput loss with a 65.5% power savings. 2017-09-20 English text Ohio University / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1500992706350957 http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1500992706350957 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws. |
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NDLTD |
| language |
English |
| sources |
NDLTD |
| topic |
Computer Engineering Electrical Engineering CPU GPU Heterogeneous Network on Chip Photonic Machine Learning Dynamic bandwidth scaling Dynamic power scaling |
| spellingShingle |
Computer Engineering Electrical Engineering CPU GPU Heterogeneous Network on Chip Photonic Machine Learning Dynamic bandwidth scaling Dynamic power scaling Van Winkle, Scott E. Dynamic Bandwidth and Laser Scaling for CPU-GPU Heterogenous Network-on-Chip Architectures |
| author |
Van Winkle, Scott E. |
| author_facet |
Van Winkle, Scott E. |
| author_sort |
Van Winkle, Scott E. |
| title |
Dynamic Bandwidth and Laser Scaling for CPU-GPU Heterogenous Network-on-Chip Architectures |
| title_short |
Dynamic Bandwidth and Laser Scaling for CPU-GPU Heterogenous Network-on-Chip Architectures |
| title_full |
Dynamic Bandwidth and Laser Scaling for CPU-GPU Heterogenous Network-on-Chip Architectures |
| title_fullStr |
Dynamic Bandwidth and Laser Scaling for CPU-GPU Heterogenous Network-on-Chip Architectures |
| title_full_unstemmed |
Dynamic Bandwidth and Laser Scaling for CPU-GPU Heterogenous Network-on-Chip Architectures |
| title_sort |
dynamic bandwidth and laser scaling for cpu-gpu heterogenous network-on-chip architectures |
| publisher |
Ohio University / OhioLINK |
| publishDate |
2017 |
| url |
http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1500992706350957 |
| work_keys_str_mv |
AT vanwinklescotte dynamicbandwidthandlaserscalingforcpugpuheterogenousnetworkonchiparchitectures |
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1719452746327785472 |