High Performance Shared Memory Networking in Future Many-core Architectures UsingOptical Interconnects

Bibliographic Details
Main Author:	Neel, Brian
Language:	English
Published:	Ohio University / OhioLINK 2014
Subjects:	Computer Engineering Network-on-chips Silicon Photonics
Online Access:	http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1397488118

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spelling	ndltd-OhioLink-oai-etd.ohiolink.edu-ohiou13974881182021-08-03T06:23:49Z High Performance Shared Memory Networking in Future Many-core Architectures UsingOptical Interconnects Neel, Brian Computer Engineering Network-on-chips Silicon Photonics As the technology node continues to scale down in feature size, there is an increase in the number of transistors that can be integrated on a single chip. The growth in the number of transistors permit scalable multi-core designs that continue to provide performance benefits in consumer electronics, servers, supercomputers, and datacenters. Since processors with tens to hundreds of cores are available on the market today, current research is focused on developing future generations of many-core architectures that can reach hundreds to thousands of cores. Kilo-core designs provide many performance benefits such as improved throughput and execution time, however, they are limited by the network connecting all the cores. Network diameter, the maximum hops between any two distant nodes, impacts latency and power of the network. Minimizing network diameter is a critical network parameter especially in large scale networks. Metallic links can provide the necessary bandwidth, however, this can lead to power constraints as metal wires grow in power due to increased capacitance and crosstalk. Therefore, it is imperative to leverage new technologies such as optics in order to improve future network designs. Optical technology is compatible with complementary metal oxide semiconductors (CMOS) and can provide performance benefits such as high bandwidth density (Terabits per second) and low energy consumption on the order of picojoules per bit. In this thesis, optical technology is used to create a network design called SPRINT that scales to 1024 cores with a reduced hop count (4), low energy (~200 nJ/b), and high bandwidth (10 Gb/s/wavelength). SPRINT uses micro-ring resonators (MRR) to design optical crossbars between switches that act as an arrayed waveguide grating (AWG) design. AWG switches provide increased communication with cores in the same dimension by allowing them to communicate on separate wavelengths. Multiple wavelengths can be placed in the same waveguide with wavelength division multiplexing (WDM) providing increased bandwidth between cores. SPRINT doubles throughput and reduces energy by 40-70\% when compared to state-of-the-art electrical networks. 2014-06-11 English text Ohio University / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1397488118 http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1397488118 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection	NDLTD
language	English
sources	NDLTD
topic	Computer Engineering Network-on-chips Silicon Photonics
spellingShingle	Computer Engineering Network-on-chips Silicon Photonics Neel, Brian High Performance Shared Memory Networking in Future Many-core Architectures UsingOptical Interconnects
author	Neel, Brian
author_facet	Neel, Brian
author_sort	Neel, Brian
title	High Performance Shared Memory Networking in Future Many-core Architectures UsingOptical Interconnects
title_short	High Performance Shared Memory Networking in Future Many-core Architectures UsingOptical Interconnects
title_full	High Performance Shared Memory Networking in Future Many-core Architectures UsingOptical Interconnects
title_fullStr	High Performance Shared Memory Networking in Future Many-core Architectures UsingOptical Interconnects
title_full_unstemmed	High Performance Shared Memory Networking in Future Many-core Architectures UsingOptical Interconnects
title_sort	high performance shared memory networking in future many-core architectures usingoptical interconnects
publisher	Ohio University / OhioLINK
publishDate	2014
url	http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1397488118
work_keys_str_mv	AT neelbrian highperformancesharedmemorynetworkinginfuturemanycorearchitecturesusingopticalinterconnects
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High Performance Shared Memory Networking in Future Many-core Architectures UsingOptical Interconnects

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