FPGA Based Multi-core Architectures for Deep Learning Networks

FPGA Based Multi-core Architectures for Deep Learning Networks

Bibliographic Details
Main Author: Chen, Hua
Language:English
Published: University of Dayton / OhioLINK 2015
Subjects:
Electrical Engineering
Deep learning network
FPGA
neuromorphic processor
Wormhole router
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449417091
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spelling ndltd-OhioLink-oai-etd.ohiolink.edu-dayton14494170912021-08-03T06:34:23Z FPGA Based Multi-core Architectures for Deep Learning Networks Chen, Hua Electrical Engineering Deep learning network FPGA neuromorphic processor Wormhole router Deep learning a large scalable network architecture based on neural network. It is currently an extremely active research area in machine learning and pattern recognition society. They have diverse uses including pattern recognition, signal processing, image processing, image compression, classification of remote sensing data, and big data processing. Interest in specialized architectures for accelerating deep learning networks has increased significantly because of their ability to reduce power, increase performance, and allow fault tolerant computing. Specialized neuromorphic architectures could provide high performance at extreme low powers for these applications. This thesis concentrates on the implementation of multi-core neuromorphic network architecture on FPGA. Hardware prototyping of wormhole router unit is developed to control transmission of data packets running through between cores. Router units connect multiple cores into a large scalable network. This network is programmed on a Stratix IV FPGA board. Additionally, a memory initialization system is design inside the core to realize external network configuration. In this approaching, different applications could be mapped on the network without repeating FPGA compilation. One application called Image Edge Detection is mapped on the network. Finally this network outputs the desired image and demonstrate 3.4x run time efficiency and 3.6x energy-delay efficiency by FPGA implementation. 2015 English text University of Dayton / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449417091 http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449417091 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection NDLTD
language English
sources NDLTD
topic Electrical Engineering
Deep learning network
FPGA
neuromorphic processor
Wormhole router
spellingShingle Electrical Engineering
Deep learning network
FPGA
neuromorphic processor
Wormhole router
Chen, Hua
FPGA Based Multi-core Architectures for Deep Learning Networks
author Chen, Hua
author_facet Chen, Hua
author_sort Chen, Hua
title FPGA Based Multi-core Architectures for Deep Learning Networks
title_short FPGA Based Multi-core Architectures for Deep Learning Networks
title_full FPGA Based Multi-core Architectures for Deep Learning Networks
title_fullStr FPGA Based Multi-core Architectures for Deep Learning Networks
title_full_unstemmed FPGA Based Multi-core Architectures for Deep Learning Networks
title_sort fpga based multi-core architectures for deep learning networks
publisher University of Dayton / OhioLINK
publishDate 2015
url http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449417091
work_keys_str_mv AT chenhua fpgabasedmulticorearchitecturesfordeeplearningnetworks
_version_ 1719439263942049792

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