VaROT: Methodology for Variation-Tolerant DSP Hardware Design using Post-Silicon Truncation of Operand Width

VaROT: Methodology for Variation-Tolerant DSP Hardware Design using Post-Silicon Truncation of Operand Width

Bibliographic Details
Main Author: Kunaparaju, Keerthi
Language:English
Published: Case Western Reserve University School of Graduate Studies / OhioLINK 2011
Subjects:
Electrical Engineering
Post-Silicon Repair
DSP
Quality of Service
Operand Truncation
Yield Improvement
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=case1295638939
id ndltd-OhioLink-oai-etd.ohiolink.edu-case1295638939
record_format oai_dc
spelling ndltd-OhioLink-oai-etd.ohiolink.edu-case12956389392021-08-03T05:33:51Z VaROT: Methodology for Variation-Tolerant DSP Hardware Design using Post-Silicon Truncation of Operand Width Kunaparaju, Keerthi Electrical Engineering Post-Silicon Repair DSP Quality of Service Operand Truncation Yield Improvement <p>Dramatic improvements in semiconductor integrated circuit technology presently make it possible to integrate millions of transistors, onto a single semiconductor IC. These improvements in integration densities have been driven by aggressive scaling of technology, which has led to both increasing density and computing power.</p><p> On the flip side, constant drive towards ever decreasing feature sizes has led to a signicant increase in manufacturing cost. One of the main causes of this increase in manufacturing cost is a signicant decrease in manufacturing yield due to manufacturing losses. These manufacturing losses are due to increasing process parameter variations that CMOS devices face at nanometer scale.</p><p> Increasing device parameter variations in nanometer CMOS technologies cause large spread in circuit parameters such as delay and power, leading to parametric yield loss. For Digital Signal Processing (DSP) hardware, variations in circuit parameters can signicantly aect the Quality of Service (QoS). Post-silicon calibration and repair have emerged as an eective solution to maintain QoS in DSP chips under large process-induced parameter variations. However, existing calibration and repair approaches rely on adaptation of circuit operating parameters such as voltage, fre-quency or body bias and typically incur large delay or power overhead. In this thesis, a novel low-overhead approach of healing DSP chips by commensurately truncating the operand width based on their process shifts is presented. The proposed approach exploits the fact that critical timing paths in typical DSP datapaths originate from the least signicant bits. Hence, truncation of these bits, by setting them at constant values, can eectively reduce the delay of a unit, thereby avoiding delay failures. Efficient choice of truncation bits and values can minimize the impact of truncation on QoS. Appropriate design time modications including insertion of low-overhead truncation circuit and skewing the path delay distribution through gate sizing to maximize the delay improvement with truncation are presented.</p><p> The proposed technique is applied on two common DSP circuits, namely Discrete Cosine Transform (DCT) and Finite Impulse Response (FIR). Simulation results show signicant decrease in critical path delay with the truncation of least signicant input bits and a graceful degradation in the QoS. Also there is a large improvementin manufacturing yield (41:6%) with up to 5X savings in power compared to existing approaches like voltage scaling and body biasing.</p> 2011-03-15 English text Case Western Reserve University School of Graduate Studies / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=case1295638939 http://rave.ohiolink.edu/etdc/view?acc_num=case1295638939 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection NDLTD
language English
sources NDLTD
topic Electrical Engineering
Post-Silicon Repair
DSP
Quality of Service
Operand Truncation
Yield Improvement
spellingShingle Electrical Engineering
Post-Silicon Repair
DSP
Quality of Service
Operand Truncation
Yield Improvement
Kunaparaju, Keerthi
VaROT: Methodology for Variation-Tolerant DSP Hardware Design using Post-Silicon Truncation of Operand Width
author Kunaparaju, Keerthi
author_facet Kunaparaju, Keerthi
author_sort Kunaparaju, Keerthi
title VaROT: Methodology for Variation-Tolerant DSP Hardware Design using Post-Silicon Truncation of Operand Width
title_short VaROT: Methodology for Variation-Tolerant DSP Hardware Design using Post-Silicon Truncation of Operand Width
title_full VaROT: Methodology for Variation-Tolerant DSP Hardware Design using Post-Silicon Truncation of Operand Width
title_fullStr VaROT: Methodology for Variation-Tolerant DSP Hardware Design using Post-Silicon Truncation of Operand Width
title_full_unstemmed VaROT: Methodology for Variation-Tolerant DSP Hardware Design using Post-Silicon Truncation of Operand Width
title_sort varot: methodology for variation-tolerant dsp hardware design using post-silicon truncation of operand width
publisher Case Western Reserve University School of Graduate Studies / OhioLINK
publishDate 2011
url http://rave.ohiolink.edu/etdc/view?acc_num=case1295638939
work_keys_str_mv AT kunaparajukeerthi varotmethodologyforvariationtolerantdsphardwaredesignusingpostsilicontruncationofoperandwidth
_version_ 1719421809552523264

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