An FPGA Abstraction Layer for the Space Telecommunications Radio System

An FPGA Abstraction Layer for the Space Telecommunications Radio System

Bibliographic Details
Main Author: Nappier, Jennifer M.
Language:English
Published: Case Western Reserve University School of Graduate Studies / OhioLINK 2009
Subjects:
Electrical Engineering
waveforms
space communication
software reuse
firmware
FPGA
HAL
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=case1227033556
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spelling ndltd-OhioLink-oai-etd.ohiolink.edu-case12270335562021-08-03T05:32:55Z An FPGA Abstraction Layer for the Space Telecommunications Radio System Nappier, Jennifer M. Electrical Engineering waveforms space communication software reuse firmware FPGA HAL The Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the specialized signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. The extension of STRS to the SSP hardware will promote easier waveform reconfiguration and reuse. Extensions of the STRS Architecture Standard in the field programmable gate array (FPGA) were proposed. The extensions included a standard hardware abstraction layer for firmware in FPGAs. Current existing FPGA hardware abstraction layer standards were researched. These standards included the Joint Tactical Radio System (JTRS) Modem Hardware Abstraction Layer (MHAL), the WISHBONE Architecture, and the Open Core Protocol (OCP). The proposed STRS hardware abstraction layer was designed to provide standardized interfaces to the STRS waveform application running on the FPGA. Therefore, the waveform developer would not have to know a lot of information about the rest of the SDR platform. This standard hardware abstraction layer was called the Firmware Developer Interface (FDI). The FDI was implemented and tested on a laboratory breadboard SDR. The implementation and testing of the FDI on a laboratory breadboard SDR will be discussed. 2009 English text Case Western Reserve University School of Graduate Studies / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=case1227033556 http://rave.ohiolink.edu/etdc/view?acc_num=case1227033556 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection NDLTD
language English
sources NDLTD
topic Electrical Engineering
waveforms
space communication
software reuse
firmware
FPGA
HAL
spellingShingle Electrical Engineering
waveforms
space communication
software reuse
firmware
FPGA
HAL
Nappier, Jennifer M.
An FPGA Abstraction Layer for the Space Telecommunications Radio System
author Nappier, Jennifer M.
author_facet Nappier, Jennifer M.
author_sort Nappier, Jennifer M.
title An FPGA Abstraction Layer for the Space Telecommunications Radio System
title_short An FPGA Abstraction Layer for the Space Telecommunications Radio System
title_full An FPGA Abstraction Layer for the Space Telecommunications Radio System
title_fullStr An FPGA Abstraction Layer for the Space Telecommunications Radio System
title_full_unstemmed An FPGA Abstraction Layer for the Space Telecommunications Radio System
title_sort fpga abstraction layer for the space telecommunications radio system
publisher Case Western Reserve University School of Graduate Studies / OhioLINK
publishDate 2009
url http://rave.ohiolink.edu/etdc/view?acc_num=case1227033556
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