ANALOG CIRCUIT SIZING USING MACHINE LEARNING BASED TRANSISTORCIRCUIT MODEL

ANALOG CIRCUIT SIZING USING MACHINE LEARNING BASED TRANSISTORCIRCUIT MODEL

Bibliographic Details
Main Author: Bagheri Rajeoni, Alireza
Language:English
Published: University of Akron / OhioLINK 2021
Subjects:
Electrical Engineering
ANALOG CIRCUIT SIZING
MACHINE LEARNING
TRANSISTOR CIRCUIT MODEL
REGRESSION
CMOS
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=akron1609428170125214
id ndltd-OhioLink-oai-etd.ohiolink.edu-akron1609428170125214
record_format oai_dc
spelling ndltd-OhioLink-oai-etd.ohiolink.edu-akron16094281701252142021-08-03T07:16:40Z ANALOG CIRCUIT SIZING USING MACHINE LEARNING BASED TRANSISTORCIRCUIT MODEL Bagheri Rajeoni, Alireza Electrical Engineering ANALOG CIRCUIT SIZING MACHINE LEARNING TRANSISTOR CIRCUIT MODEL REGRESSION CMOS In this work, a new method for designing an analog circuit for deep sub-micronCMOS fabrication processes is proposed. The proposed method leverages the regressionalgorithms with the transistor circuit model to size a transistor in 0.18 µm technology fastand without using simulation software. Threshold voltage, output resistance, and theproduct of mobility and oxide capacitance are key parameters in the transistor circuit modelto size a transistor. For nano-scale transistors, however, these parameters are nonlinear withrespect to electrical and physical characteristics of transistors and circuit simulator isneeded to find the value of these parameters and therefore the design time increases.Regression analysis is utilized to predict values of these parameters. We demonstrate theperformance of the proposed method by designing a Current Feedback InstrumentationalAmplifier (CFIA). We show that the presented method accomplishes higher than 90%accuracy in predicting the desired value of W. It reduces the design time over 97%compared to conventional methods. The designed circuit using the proposed methodconsumes 5.76 µW power and has a Common Mode Rejection Ratio (CMRR) of 35.83 dBand it results in achieving 8.17 V/V gain. 2021-02-04 English text University of Akron / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=akron1609428170125214 http://rave.ohiolink.edu/etdc/view?acc_num=akron1609428170125214 unrestricted This thesis or dissertation is protected by copyright: some rights reserved. It is licensed for use under a Creative Commons license. Specific terms and permissions are available from this document's record in the OhioLINK ETD Center.
collection NDLTD
language English
sources NDLTD
topic Electrical Engineering
ANALOG CIRCUIT SIZING
MACHINE LEARNING
TRANSISTOR CIRCUIT MODEL
REGRESSION
CMOS
spellingShingle Electrical Engineering
ANALOG CIRCUIT SIZING
MACHINE LEARNING
TRANSISTOR CIRCUIT MODEL
REGRESSION
CMOS
Bagheri Rajeoni, Alireza
ANALOG CIRCUIT SIZING USING MACHINE LEARNING BASED TRANSISTORCIRCUIT MODEL
author Bagheri Rajeoni, Alireza
author_facet Bagheri Rajeoni, Alireza
author_sort Bagheri Rajeoni, Alireza
title ANALOG CIRCUIT SIZING USING MACHINE LEARNING BASED TRANSISTORCIRCUIT MODEL
title_short ANALOG CIRCUIT SIZING USING MACHINE LEARNING BASED TRANSISTORCIRCUIT MODEL
title_full ANALOG CIRCUIT SIZING USING MACHINE LEARNING BASED TRANSISTORCIRCUIT MODEL
title_fullStr ANALOG CIRCUIT SIZING USING MACHINE LEARNING BASED TRANSISTORCIRCUIT MODEL
title_full_unstemmed ANALOG CIRCUIT SIZING USING MACHINE LEARNING BASED TRANSISTORCIRCUIT MODEL
title_sort analog circuit sizing using machine learning based transistorcircuit model
publisher University of Akron / OhioLINK
publishDate 2021
url http://rave.ohiolink.edu/etdc/view?acc_num=akron1609428170125214
work_keys_str_mv AT bagherirajeonialireza analogcircuitsizingusingmachinelearningbasedtransistorcircuitmodel
_version_ 1719457794538602496

Similar Items