Modeling of a Three Layer Coated Nanowire Transistor
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University of Akron / OhioLINK
2010
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| Online Access: | http://rave.ohiolink.edu/etdc/view?acc_num=akron1291935683 |
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ndltd-OhioLink-oai-etd.ohiolink.edu-akron12919356832021-08-03T05:26:32Z Modeling of a Three Layer Coated Nanowire Transistor Kucherlapati, Naga Swathi Electrical Engineering nanowire transistor <p>The integration density of silicon transistors is increasing from the past few decades due to rapid miniaturization. Bipolar junction transistors (BJT) successfully replaced vacuum tubes but the main problem using BJT's include speed and current gain. To further improve integration density, speed and current gain nanoscale transistors are being explored. This thesis discusses the design of nanowire transistor with 50nm or less base width. It assumes that the device structure is cylindrical in shape which is different from BJT. The method of implementation in nanoscale is adopted from basic macroscale from a classical paper by Rittner.</p><p>Regardless of the evolution, the theory behind the transistor dates back to 1947, by the discovery of Shockley. Rittner's paper examines approximations used in shockley's results and these examinations are used as analysis tools in this work. This work is an extension to Rittner's paper, it numerically solves the nonlinear equation for bipolar junction transistor. It also derives nanowire transistor linear and nonlinear equations based on the mathematical formulations of bipolar junction transistor. Solutions to nanowire linear and nonlinear equations are compared and justified in light of the results from BJT.</p> 2010 English text University of Akron / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=akron1291935683 http://rave.ohiolink.edu/etdc/view?acc_num=akron1291935683 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws. |
| collection |
NDLTD |
| language |
English |
| sources |
NDLTD |
| topic |
Electrical Engineering nanowire transistor |
| spellingShingle |
Electrical Engineering nanowire transistor Kucherlapati, Naga Swathi Modeling of a Three Layer Coated Nanowire Transistor |
| author |
Kucherlapati, Naga Swathi |
| author_facet |
Kucherlapati, Naga Swathi |
| author_sort |
Kucherlapati, Naga Swathi |
| title |
Modeling of a Three Layer Coated Nanowire Transistor |
| title_short |
Modeling of a Three Layer Coated Nanowire Transistor |
| title_full |
Modeling of a Three Layer Coated Nanowire Transistor |
| title_fullStr |
Modeling of a Three Layer Coated Nanowire Transistor |
| title_full_unstemmed |
Modeling of a Three Layer Coated Nanowire Transistor |
| title_sort |
modeling of a three layer coated nanowire transistor |
| publisher |
University of Akron / OhioLINK |
| publishDate |
2010 |
| url |
http://rave.ohiolink.edu/etdc/view?acc_num=akron1291935683 |
| work_keys_str_mv |
AT kucherlapatinagaswathi modelingofathreelayercoatednanowiretransistor |
| _version_ |
1719420125822582784 |