| Summary: | The recent advances in VLSI technology have facilitated feature shrinking
and hence a rapid increase in the levels of integration at the chip level. This increase
in the level of integration has brought along with it a host of other constraints, the
most crucial being timing management and increased power dissipation. Such
constraints potentially prevent the full exploitation of the increased processing power
made possible by technological advances.
Timing in complex digital systems has traditionally been managed by using
a global clock, controlled by which all the actions take place in lock-step. An alternative
means of managing timing, called self-timing, simplifies the problems of timing management
and results in a reduced power dissipation of complex digital systems. Systems
designed using this self-timed or asynchronous protocol, work on a principle of handshaking,
running at their own speed, governed by local timers and the availability
of data on which to work. However, this hand-shaking introduces an overhead both
in terms of hardware and computational speed.
The work presented here examines the implementation of an adder, called
a Parallel Half-Adder (PHA), which gains its speed by exploiting the power of asynchrony to calculate the sum. The adder has been implemented in the form of a tunable
micropipeline and compared to traditional adders in terms of hardware complexity
and speed. Comparable results have been obtained, implying that the overhead due
to hand shaking is justified and the performance improvements due to self-timing
can be fully exploited. The design of an array divider using the PHA has also been
presented. === Graduation date: 1995
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