Memory optimization for a parallel sorting hardware architecture

• Main Author: Beyer, Dale A.
• Other Authors: Lu, Shih-Lien
• Language: en_US
• Published: 2012
• Subjects: Sorting (Electronic computers); Parallel processing (Electronic computers); Computer algorithms
• Online Access: http://hdl.handle.net/1957/33781

Sorting is one of the more computationally intensive tasks a computer performs. One of the most effective ways to speed up the task of sorting is by using parallel algorithms. When implementing a parallel algorithm, the designer has to make several decisions. Among the decisions are the algorithm and the physical implementation of the algorithm. A dedicated hardware solution is often physically quicker than a software solution. In this thesis, we will investigate the optimization of a hardware implementation of max-min sort. I propose an optimization to the data structures used in the algorithm. The new data structure allows quicker sorting by changing the basic workings of the max-min sort. The results are presented by comparing the new data structure with the original data structure. The thesis also discusses the design and performance issues related to implementing the algorithm in hardware. === Graduation date: 1998