| Summary: | Traditionally sinusoidal signal generation has been implemented with purely analog circuits such as phase-locked loops. The alternative of using a digital system to perform this signal generation has previously been unattractive due to limitations in clock frequency and size. However, recent advancements in sub-micron fabrication techniques have made the digital alternative tractable. The advantages of a digitally implemented signal frequency synthesizer include finer control of output frequency, reduced frequency drift due to part degradation over time, and faster response time for frequency change.
Digital frequency synthesis has been previously realized using the Tierney, Rader, and Gold phase accumulator architecture. This method utilizes a variable-increment digital integrator that is input to a read-only memory. This memory then generates a quantized amplitude value. This thesis presents an alternative method for digital frequency synthesis based on circular interpolation and compares it to the performance of a comparable phase-accumulator structure for varying bit accuracies of phase. The comparison of transistor count and required die-size for each method reveals a lower requirement of both resources in the case of the new circle interpolator. Evaluation of the discrete-time spectral purity of synthesized signals also demonstrates less out of band noise in the new design. Finally, analysis
of energy efficiency shows the new design to be generally optimal compared to the reference design. === Graduation date: 2001
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