| Summary: | Pipelined analog to digital converters (ADCs) are very important building
blocks in many electronic systems such as high quality video systems, high
performance digital communication systems and high speed data acquisition systems.
The rapid development of these applications is driving the design of pipeline ADCs
towards higher speed, higher dynamic range, lower power consumption and lower
power supply voltage with the CMOS technology scaling. This trend poses great
challenges to conventional pipelined ADC designs which rely on high-gain
operational amplifiers (opamps) and well matched capacitors to achieve high accuracy. In this thesis, two novel accuracy improvement techniques to overcome the
accuracy limit set by analog building blocks (opamps and capacitors) in the context of
low-voltage and high-speed pipelined ADC design are presented. One is the time-shifted
correlated double sampling (CDS) technique which addresses the finite opamp
gain effect and the other is the radix-based background digital calibration technique
which can take care of both finite opamp gain and capacitor mismatch. These methods
are simple, easy to implement and power efficient. The effectiveness of the proposed
techniques is demonstrated in simulation as well as in experiment.
Two prototype ADCs have been designed and fabricated in 0.18μm CMOS
technology as the experimental verification of the proposed techniques. The first ADC
is a 1.8V 10-bit pipeline ADC which incorporated the time-shifted CDS technique to
boost the effective gain of the amplifiers. Much better gain-bandwidth tradeoff in
amplifier design is achieved with this gain boosting. Measurement results show total
power consumption of 67mW at 1.8V when operating at 100MSPS. The SNR, SNDR
and SFDR are 55dB, 54dB and 65dB respectively given a 1MHz input signal. The
second one is a 0.9V 12-bit two-stage cyclic ADC which employed a novel
correlation-based background calibration to enhance the linearity. The linearity limit
set by the capacitor mismatches, finite opamp gain effects is exceeded. After
calibration, the SFDR is improved by about 33dB and exceeds 80dB. The power
consumption is 12mW from 0.9V supply when operating at 2MSPS. === Graduation date: 2004
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