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ndltd-NEU--neu-933
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oai_dc
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ndltd-NEU--neu-9332021-05-26T05:10:57Z45nm CMOS, low jitter, all-digital delay locked loop with a circuit to dynamically vary phase to achieve fast lockThe objective of the thesis is to address the problem of clock skew between two different clock domains in modern day microprocessors due to the process, voltage and temperature (PVT) variations. In order to mitigate the misalignment of the clocks in the different clock domains, a delay line is added in all but the reference clock domain. These delay lines add or subtract the delay (as necessary) to keep the clocks continuously aligned to a common reference clock delay. This ensures error free data transfer between any two clock domains.http://hdl.handle.net/2047/d20002106
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NDLTD
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NDLTD
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| description |
The objective of the thesis is to address the problem of clock skew between two different clock domains in modern day microprocessors due to the process, voltage and temperature (PVT) variations. In order to mitigate the misalignment of the clocks in the different clock domains, a delay line is added in all but the reference clock domain. These delay lines add or subtract the delay (as necessary) to keep the clocks continuously aligned to a common reference clock delay. This
ensures error free data transfer between any two clock domains.
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| title |
45nm CMOS, low jitter, all-digital delay locked loop with a circuit to dynamically vary phase to achieve fast lock
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| spellingShingle |
45nm CMOS, low jitter, all-digital delay locked loop with a circuit to dynamically vary phase to achieve fast lock
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| title_short |
45nm CMOS, low jitter, all-digital delay locked loop with a circuit to dynamically vary phase to achieve fast lock
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| title_full |
45nm CMOS, low jitter, all-digital delay locked loop with a circuit to dynamically vary phase to achieve fast lock
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| title_fullStr |
45nm CMOS, low jitter, all-digital delay locked loop with a circuit to dynamically vary phase to achieve fast lock
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| title_full_unstemmed |
45nm CMOS, low jitter, all-digital delay locked loop with a circuit to dynamically vary phase to achieve fast lock
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| title_sort |
45nm cmos, low jitter, all-digital delay locked loop with a circuit to dynamically vary phase to achieve fast lock
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| publishDate |
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| url |
http://hdl.handle.net/2047/d20002106
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| _version_ |
1719406473817096192
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