Phase unwrapping on recongurable hardware and graphics processors

Phase unwrapping is the process of converting discontinuous phase data into a continuous image. This procedure is required by any imaging technology that uses phase data such as MRI, SAR or OQM microscopy. Such algorithms often take a significant amount of time to process on a general purpose comput...

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spelling ndltd-NEU--neu-12592021-05-25T05:09:38ZPhase unwrapping on recongurable hardware and graphics processorsPhase unwrapping is the process of converting discontinuous phase data into a continuous image. This procedure is required by any imaging technology that uses phase data such as MRI, SAR or OQM microscopy. Such algorithms often take a significant amount of time to process on a general purpose computer, rendering it difficult to process large quantities of information. This thesis focuses on implementing a specific phase unwrapping algorithm known as Minimum LP norm unwrapping on a Field Programmable Gate Array (FPGA) and a Graphics Processing Unit (GPU) for the purpose of acceleration. The computation required involves a matrix preconditioner (based on a DCT transform) and a conjugate gradient calculation along with a few other matrix operations. These functions are partitioned to run on the host or the accelerator depending on the capabilities of the accelerator. The trade-offs between the two platforms are analyzed and compared to a General Purpose Processor (GPP) in terms of performance, power and cost.http://hdl.handle.net/2047/d10017252
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description Phase unwrapping is the process of converting discontinuous phase data into a continuous image. This procedure is required by any imaging technology that uses phase data such as MRI, SAR or OQM microscopy. Such algorithms often take a significant amount of time to process on a general purpose computer, rendering it difficult to process large quantities of information. This thesis focuses on implementing a specific phase unwrapping algorithm known as Minimum LP norm unwrapping on a Field Programmable Gate Array (FPGA) and a Graphics Processing Unit (GPU) for the purpose of acceleration. The computation required involves a matrix preconditioner (based on a DCT transform) and a conjugate gradient calculation along with a few other matrix operations. These functions are partitioned to run on the host or the accelerator depending on the capabilities of the accelerator. The trade-offs between the two platforms are analyzed and compared to a General Purpose Processor (GPP) in terms of performance, power and cost.
title Phase unwrapping on recongurable hardware and graphics processors
spellingShingle Phase unwrapping on recongurable hardware and graphics processors
title_short Phase unwrapping on recongurable hardware and graphics processors
title_full Phase unwrapping on recongurable hardware and graphics processors
title_fullStr Phase unwrapping on recongurable hardware and graphics processors
title_full_unstemmed Phase unwrapping on recongurable hardware and graphics processors
title_sort phase unwrapping on recongurable hardware and graphics processors
publishDate
url http://hdl.handle.net/2047/d10017252
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