| Summary: | <p>Dynamic partial reconfiguration of FPGAs allows systems to autonomously alter sections of their design during runtime based on the state of the system. This functionality provides size, weight, and power benefits that are useful in extreme environments such as space. Therefore, NASA has requested research into the feasibility of using a commercial off-the-shelf software flow to convert a static HDL design to support partial reconfiguration. This project presents an analysis of this conversion process using the Xilinx Partial Reconfiguration Flow to convert the static design for the ITU G.729 Voice Decoder. This paper explores the design modifications that must be made to allow for partial reconfiguration. Furthermore, an in-depth description of how to set up the hardware platform to support the HDL application is provided. Finally, timing and size data are presented and analyzed to empirically show the benefits and limitations of using dynamic partial reconfiguration.</p>
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