| Summary: | The lack of high quality factor integrated inductors is a significant impediment to realizing high performance Radio Frequency Integrated Circuits (RFICs) within conventional digital CMOS. While passive spiral inductors continue to improve with different approaches and fabrication techniques, they tend to be large and lossy. Therefore, an accurate inductance with high quality factor and small chip area would be an extremely useful component for RFIC designers. The focus of this thesis is realizing accurate, high-quality factor inductance using an active circuit approach for implementation in RFIC applications. It is demonstrated that, when implemented in a conventional digital CMOS process, the standard active inductor topology suffers greatly, in terms of performance and stability, over the transistor process corners and thus some form of an automatic tuning approach is necessary for these devices to be used reliably. Consequently, a master-slave tuning circuit was designed and included in order to tune the active inductor over the process corners of the AMIS C5 process. Simulated results are presented that verify the functionality of the proposed active inductor topology. In addition, simulation results utilizing an automatically tuned inductor within a two-way lumped element Wilkinson power divider demonstrates the utility of the chosen approach. Considerations for adapting this approach for use in a scaled CMOS process are discussed.
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