A high aspect-ratio silicon substrate-via technology and applications

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000. === Includes bibliographical references (p. 85-90). === Substrate vias are widely used in GaAs microwave and millimeter-wave ICs to provide low impedance ground connections. As silicon R...

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Main Author: Wu, Joyce H. (Joyce Hsia-Sing), 1974-
Other Authors: Jesús A. del Alamo.
Format: Others
Language:English
Published: Massachusetts Institute of Technology 2005
Subjects:
Online Access:http://hdl.handle.net/1721.1/8811
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spelling ndltd-MIT-oai-dspace.mit.edu-1721.1-88112019-05-02T15:41:54Z A high aspect-ratio silicon substrate-via technology and applications Wu, Joyce H. (Joyce Hsia-Sing), 1974- Jesús A. del Alamo. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000. Includes bibliographical references (p. 85-90). Substrate vias are widely used in GaAs microwave and millimeter-wave ICs to provide low impedance ground connections. As silicon RFICs strive for high-frequency operation, it becomes increasingly important to reduce all extrinsic parasitics. Of particular concern is the MOSFET source or BJT emitter impedance, which greatly affects the gain of RF amplifiers. To address this, we have developed a through-wafer via technology for silicon, which allows the implementation of high-aspect ratio, low-impedance ground connections. The fabrication of these vias involves three main steps: (1) anisotropic DRIE to etch the vias, (2) PECVD silicon nitride deposition to form an insulating, barrier liner, and (3) copper electroplating to fill the via. Since our vias incorporate an insulating liner, this through-wafer via technology could also be used to distribute power and ground in logic circuits and MEMS. We have demonstrated vias with an aspect ratio as high as 14:1 and an inductance that approaches the theoretically expected value. Our via technology can also be exploited to reduce crosstalk and improve subsystem isolation in RF System-on-a-Chip applications. High crosstalk immunity is critical to enable one-chip systems integrating noisy logic with sensitive low-noise amplifier and analog circuitry. Using our substrate-via technology, we have implemented a novel Faraday cage isolation scheme that is successful in suppressing crosstalk by over 20 dB at 1 GHz at a distance of 100 [mu]m. by Joyce H. Wu. S.M. 2005-08-23T15:31:34Z 2005-08-23T15:31:34Z 2000 2000 Thesis http://hdl.handle.net/1721.1/8811 48253155 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 90 p. 6898696 bytes 6898457 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology
collection NDLTD
language English
format Others
sources NDLTD
topic Electrical Engineering and Computer Science.
spellingShingle Electrical Engineering and Computer Science.
Wu, Joyce H. (Joyce Hsia-Sing), 1974-
A high aspect-ratio silicon substrate-via technology and applications
description Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000. === Includes bibliographical references (p. 85-90). === Substrate vias are widely used in GaAs microwave and millimeter-wave ICs to provide low impedance ground connections. As silicon RFICs strive for high-frequency operation, it becomes increasingly important to reduce all extrinsic parasitics. Of particular concern is the MOSFET source or BJT emitter impedance, which greatly affects the gain of RF amplifiers. To address this, we have developed a through-wafer via technology for silicon, which allows the implementation of high-aspect ratio, low-impedance ground connections. The fabrication of these vias involves three main steps: (1) anisotropic DRIE to etch the vias, (2) PECVD silicon nitride deposition to form an insulating, barrier liner, and (3) copper electroplating to fill the via. Since our vias incorporate an insulating liner, this through-wafer via technology could also be used to distribute power and ground in logic circuits and MEMS. We have demonstrated vias with an aspect ratio as high as 14:1 and an inductance that approaches the theoretically expected value. Our via technology can also be exploited to reduce crosstalk and improve subsystem isolation in RF System-on-a-Chip applications. High crosstalk immunity is critical to enable one-chip systems integrating noisy logic with sensitive low-noise amplifier and analog circuitry. Using our substrate-via technology, we have implemented a novel Faraday cage isolation scheme that is successful in suppressing crosstalk by over 20 dB at 1 GHz at a distance of 100 [mu]m. === by Joyce H. Wu. === S.M.
author2 Jesús A. del Alamo.
author_facet Jesús A. del Alamo.
Wu, Joyce H. (Joyce Hsia-Sing), 1974-
author Wu, Joyce H. (Joyce Hsia-Sing), 1974-
author_sort Wu, Joyce H. (Joyce Hsia-Sing), 1974-
title A high aspect-ratio silicon substrate-via technology and applications
title_short A high aspect-ratio silicon substrate-via technology and applications
title_full A high aspect-ratio silicon substrate-via technology and applications
title_fullStr A high aspect-ratio silicon substrate-via technology and applications
title_full_unstemmed A high aspect-ratio silicon substrate-via technology and applications
title_sort high aspect-ratio silicon substrate-via technology and applications
publisher Massachusetts Institute of Technology
publishDate 2005
url http://hdl.handle.net/1721.1/8811
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