| Summary: | Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000. === Includes bibliographical references (p. 85-90). === Substrate vias are widely used in GaAs microwave and millimeter-wave ICs to provide low impedance ground connections. As silicon RFICs strive for high-frequency operation, it becomes increasingly important to reduce all extrinsic parasitics. Of particular concern is the MOSFET source or BJT emitter impedance, which greatly affects the gain of RF amplifiers. To address this, we have developed a through-wafer via technology for silicon, which allows the implementation of high-aspect ratio, low-impedance ground connections. The fabrication of these vias involves three main steps: (1) anisotropic DRIE to etch the vias, (2) PECVD silicon nitride deposition to form an insulating, barrier liner, and (3) copper electroplating to fill the via. Since our vias incorporate an insulating liner, this through-wafer via technology could also be used to distribute power and ground in logic circuits and MEMS. We have demonstrated vias with an aspect ratio as high as 14:1 and an inductance that approaches the theoretically expected value. Our via technology can also be exploited to reduce crosstalk and improve subsystem isolation in RF System-on-a-Chip applications. High crosstalk immunity is critical to enable one-chip systems integrating noisy logic with sensitive low-noise amplifier and analog circuitry. Using our substrate-via technology, we have implemented a novel Faraday cage isolation scheme that is successful in suppressing crosstalk by over 20 dB at 1 GHz at a distance of 100 [mu]m. === by Joyce H. Wu. === S.M.
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