An asynchronous,low-power architecture for interleaved neural stimulation, using envelope and phase information
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007. === Includes bibliographical references (p. 122-124). === This thesis describes a low-power cochlear-implant processor chip and a charge-balanced stimulation chip that together form a...
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| Format: | Others |
| Language: | English |
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Massachusetts Institute of Technology
2008
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| Online Access: | http://hdl.handle.net/1721.1/40512 |