| Summary: | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. === Includes bibliographical references (p. 233-240). === The majority of photodetectors presented in the literature, or available commercially, have dimensions on the order of 50 Ym or smaller, suitable for glass multimode or single mode fibre applications. The recent successful commercialisation of very large core diameter plastic optical fibre in systems based around 650 nm emitters, as well as the recent emergence of new polymer materials enabling relatively low loss at the more standard 780 nm and 850 nm wavelengths, has exposed the need for integrated photodetectors with dimensions well above 100 /m and capable of bitrates from 250 Mb/s for low-cost consumer applications to multiple Gb/s for high performance short reach interconnects. This size-performance regime has been largely ignored until now. This work examines interdigitated detector structures in multiple material systems by measurement and simulation. An optoelectronic frequency response measurement system was designed and implemented for this work, allowing measurement up to 8 GHz using 850 nm or 1550 nm sources. The full expression for frequency response of diffusion current under different illumination scenarios was derived, a topic normally omitted in the discussion of photodetectors, and applied to the analysis of device measurements. === (cont.) Silicon detectors of various geometries were fabricated, with measured bandwidths at 5 V reverse bias up to 2 GHz for 200 ym diameter devices and 4 GHz for 50 and 100 ym diameter devices. The latter is the highest bandwidth reported for a silicon detector fabricated in a CMOS-compatible process and biased at a practically accessible voltage. Device performance was confirmed by simulation, and a novel structure is proposed featuring a buried junction on SOI determined by simulation to have twice as high a responsivity-bandwidth product as the best reported devices fabricated on high resistivity SOI. The silicon device structure was modified for epitaxial germanium wafers, and devices were fabricated. The germanium devices were simulated to determine the appropriate technology scaling direction and maximum device dimensions for desired performance specifications. === by Wojciech Piotr Giziewicz. === Ph.D.
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