Clock division as a power saving strategy in a system constrained by high transmission frequency and low data rate
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005. === Includes bibliographical references (p. 63). === Systems are often restricted to have higher transmission frequency than required by their data rates. Possible constraints include...
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ndltd-MIT-oai-dspace.mit.edu-1721.1-333602019-05-02T15:57:22Z Clock division as a power saving strategy in a system constrained by high transmission frequency and low data rate Selbst, Andrew D. (Andrew David) Rahul Sarpeshkar. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005. Includes bibliographical references (p. 63). Systems are often restricted to have higher transmission frequency than required by their data rates. Possible constraints include channel attenuation, power requirements, and backward compatibility. As a result these systems have unused band- width, leading to inefficient use of power. In this thesis, I propose to slow the internal operating frequency of a cochlear implant receiver in order to reduce the internal power consumption by more than a factor of ten. I have created a new data encoding scheme, called "N-[pi] Shift Encoding", which makes clock division a viable solution. This clock division technique can be applied to other similarly constrained systems. by Andrew D. Selbst. M.Eng. 2006-07-13T15:18:08Z 2006-07-13T15:18:08Z 2005 2005 Thesis http://hdl.handle.net/1721.1/33360 62413893 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 63 p. 2281684 bytes 2284209 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
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Electrical Engineering and Computer Science. |
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Electrical Engineering and Computer Science. Selbst, Andrew D. (Andrew David) Clock division as a power saving strategy in a system constrained by high transmission frequency and low data rate |
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005. === Includes bibliographical references (p. 63). === Systems are often restricted to have higher transmission frequency than required by their data rates. Possible constraints include channel attenuation, power requirements, and backward compatibility. As a result these systems have unused band- width, leading to inefficient use of power. In this thesis, I propose to slow the internal operating frequency of a cochlear implant receiver in order to reduce the internal power consumption by more than a factor of ten. I have created a new data encoding scheme, called "N-[pi] Shift Encoding", which makes clock division a viable solution. This clock division technique can be applied to other similarly constrained systems. === by Andrew D. Selbst. === M.Eng. |
author2 |
Rahul Sarpeshkar. |
author_facet |
Rahul Sarpeshkar. Selbst, Andrew D. (Andrew David) |
author |
Selbst, Andrew D. (Andrew David) |
author_sort |
Selbst, Andrew D. (Andrew David) |
title |
Clock division as a power saving strategy in a system constrained by high transmission frequency and low data rate |
title_short |
Clock division as a power saving strategy in a system constrained by high transmission frequency and low data rate |
title_full |
Clock division as a power saving strategy in a system constrained by high transmission frequency and low data rate |
title_fullStr |
Clock division as a power saving strategy in a system constrained by high transmission frequency and low data rate |
title_full_unstemmed |
Clock division as a power saving strategy in a system constrained by high transmission frequency and low data rate |
title_sort |
clock division as a power saving strategy in a system constrained by high transmission frequency and low data rate |
publisher |
Massachusetts Institute of Technology |
publishDate |
2006 |
url |
http://hdl.handle.net/1721.1/33360 |
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AT selbstandrewdandrewdavid clockdivisionasapowersavingstrategyinasystemconstrainedbyhightransmissionfrequencyandlowdatarate |
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1719031772725903360 |