Clock division as a power saving strategy in a system constrained by high transmission frequency and low data rate

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005. === Includes bibliographical references (p. 63). === Systems are often restricted to have higher transmission frequency than required by their data rates. Possible constraints include...

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Bibliographic Details
Main Author: Selbst, Andrew D. (Andrew David)
Other Authors: Rahul Sarpeshkar.
Format: Others
Language:English
Published: Massachusetts Institute of Technology 2006
Subjects:
Online Access:http://hdl.handle.net/1721.1/33360
Description
Summary:Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005. === Includes bibliographical references (p. 63). === Systems are often restricted to have higher transmission frequency than required by their data rates. Possible constraints include channel attenuation, power requirements, and backward compatibility. As a result these systems have unused band- width, leading to inefficient use of power. In this thesis, I propose to slow the internal operating frequency of a cochlear implant receiver in order to reduce the internal power consumption by more than a factor of ten. I have created a new data encoding scheme, called "N-[pi] Shift Encoding", which makes clock division a viable solution. This clock division technique can be applied to other similarly constrained systems. === by Andrew D. Selbst. === M.Eng.