The design of an efficient hardware subroutine protocol for FPGAs
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994. === Includes bibliographical references (leaves 54-55). === by Trevor Joseph Bauer. === M.Eng.
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| Format: | Others |
| Language: | English |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/11983 |