| Summary: | Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017. === This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. === Cataloged from student-submitted PDF version of thesis. === Includes bibliographical references (pages 109-120). === The ever-increasing demand for high-performance and low-power computing warrants an investigation of technologies beyond conventional digital transistor circuits. We explore a logic device based on magnetic domain walls, which are electrically movable boundaries between oppositely magnetized domains of a wire, for applications to hardware acceleration. A domain wall logic device takes current on the input, which moves a magnetic domain wall to a position in a ferromagnetic wire, and this position is the nonvolatile data token read as an output current through a magnetic tunnel junction. The spatial resolution of discrete magnetic domain wall positions in domain wall logic devices is studied to guide memory and logic applications. Theory, numerical modeling, and experiments on in-plane and perpendicularly magnetized materials demonstrate that the bit resolution, or analog information capacity, of a magnetic nanowire with a single domain wall is limited by the self-affine statistics of the wire edge roughness. The domain wall logic device is extended further into functional design implementations, including a logic-in-memory architecture to perform deep convolutional neural network operations in a hybrid process with magnetic devices and 45 nm CMOS. A 3-terminal magnetic logic device is designed to have a 3-bit resolution, and is used in conjunction with transistors in circuit designs for an ecient logic-in-memory system that can process convolutional neural networks 10 faster than conventional digital CMOS implementations. === by Sumit Dutta. === Ph. D.
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