Cache coherent commutative operations

Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015. === This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. === Cataloged from student-s...

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Main Author: Horn, Webb H
Other Authors: Daniel Sanchez.
Format: Others
Language:English
Published: Massachusetts Institute of Technology 2016
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Online Access:http://hdl.handle.net/1721.1/100601
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spelling ndltd-MIT-oai-dspace.mit.edu-1721.1-1006012019-05-02T16:33:10Z Cache coherent commutative operations Horn, Webb H Daniel Sanchez. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015. This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. Cataloged from student-submitted PDF version of thesis. Includes bibliographical references (pages 51-57). This thesis presents Coup, a technique that reduces the cost of updates in shared memory systems. In particular, it describes a new cache coherence protocol, MEUSI, and evaluates its performance under simulation in zsim. MEUSI extends the MESI protocol to allow data to be cached in a new update-only state, reducing both block-level thrashing and on-chip network traffic under many parallel workflows. Coup permits both single-word and multi-word commutative data operations, which are implemented as x86-64 ISA extensions. To evaluate single-word instructions, this thesis presents a case study of a new reference counting scheme, and for multi-word commutative operations, this thesis describes the design of a commutative memory allocator. Coup and MEUSI confer significant benefits to the reference counting scheme and the memory allocator, both in terms of performance and ease of programming. by Webb H. Horn. M. Eng. 2016-01-04T19:57:37Z 2016-01-04T19:57:37Z 2015 2015 Thesis http://hdl.handle.net/1721.1/100601 932217720 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 57 pages application/pdf Massachusetts Institute of Technology
collection NDLTD
language English
format Others
sources NDLTD
topic Electrical Engineering and Computer Science.
spellingShingle Electrical Engineering and Computer Science.
Horn, Webb H
Cache coherent commutative operations
description Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015. === This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. === Cataloged from student-submitted PDF version of thesis. === Includes bibliographical references (pages 51-57). === This thesis presents Coup, a technique that reduces the cost of updates in shared memory systems. In particular, it describes a new cache coherence protocol, MEUSI, and evaluates its performance under simulation in zsim. MEUSI extends the MESI protocol to allow data to be cached in a new update-only state, reducing both block-level thrashing and on-chip network traffic under many parallel workflows. Coup permits both single-word and multi-word commutative data operations, which are implemented as x86-64 ISA extensions. To evaluate single-word instructions, this thesis presents a case study of a new reference counting scheme, and for multi-word commutative operations, this thesis describes the design of a commutative memory allocator. Coup and MEUSI confer significant benefits to the reference counting scheme and the memory allocator, both in terms of performance and ease of programming. === by Webb H. Horn. === M. Eng.
author2 Daniel Sanchez.
author_facet Daniel Sanchez.
Horn, Webb H
author Horn, Webb H
author_sort Horn, Webb H
title Cache coherent commutative operations
title_short Cache coherent commutative operations
title_full Cache coherent commutative operations
title_fullStr Cache coherent commutative operations
title_full_unstemmed Cache coherent commutative operations
title_sort cache coherent commutative operations
publisher Massachusetts Institute of Technology
publishDate 2016
url http://hdl.handle.net/1721.1/100601
work_keys_str_mv AT hornwebbh cachecoherentcommutativeoperations
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