Instruction scheduling and register allocation for the MCCAT

• Main Author: Zhang, Yingwei
• Other Authors: Hendren, Laurie (advisor)
• Format: Others
• Language: en
• Published: McGill University 1995
• Subjects: Computer Science.
• Online Access: http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=22832

Instruction scheduling and register allocation play very important roles in compilation techniques for high-performance computers. In this thesis we study different analyses and transformations that may affect the performance of instruction scheduling and register allocation. === An important technique for increasing code parallelism is alias analysis. Alias analysis can reduce the number of dependences in a Data Dependence Graph (DDG) by disambiguating address references. Our study shows that points-to analysis, the alias analysis method implemented in the McCAT compiler, can substantially increase parallelism in benchmarks with indirect memory references. === In this thesis we also discuss the phase ordering problem of instruction scheduling and register allocation. An integrated approach--IPS (Integrated Prepass Scheduling) is implemented in the McCAT compiler. Experimental results show that IPS is an effective way to coordinate instruction scheduling and register allocation. Postpass scheduling and BDSF (Branch Delay Slots Filling) has been also implemented. Experiments were performed to measure the effectiveness of each scheduling method and combinations of the scheduling methods. These experiments show that IPS + postpass + BDSF is the best approach for the benchmarks studied.