Towards optimazation techniques for dynamic load balancing of parallel gate level simulation
As a consequence of Moore's law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. Consequently, parallel simulation has emerged as an approach which can be both fast and cost effective. In this thesis, we...
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| Format: | Others |
| Language: | en |
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McGill University
2011
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| Online Access: | http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=104767 |