A Variable Bandwidth, Power-Scalable Optical Receiver Front-End

• Main Author: Dash, Partha Protim
• Format: Others
• Published: 2013
• Online Access: http://spectrum.library.concordia.ca/977824/1/Dash_MASc_F2013.pdf; Dash, Partha Protim <http://spectrum.library.concordia.ca/view/creators/Dash=3APartha_Protim=3A=3A.html> (2013) A Variable Bandwidth, Power-Scalable Optical Receiver Front-End. Masters thesis, Concordia University.

The tremendous growth in internet data traffic and computation power has increased demand for high-speed links in almost all communication systems. Normally, high-speed interconnects in a super computer are implemented using a short distance electrical medium such as a printed circuit board or coaxial cable. However, data transmission through an electrical medium suffers severe bandwidth limitation due to its distributed resistance, inductance and capacitance. To overcome this problem, several equalization techniques are adopted which can make the system more complex and power hungry. An efficient way to enhance the capacity of short-reach link is through the use of an optical channel rather than the band-limited electrical one. The analog front-end is the most important building block of the optical receiver as it converts the small current generated by the photodiode to a significant voltage level. In this work, we present an inductor-less, variable bandwidth, power-scalable optical receiver front-end in TSMC 65nm and 90nm CMOS with two different topologies. The front-end contains a transimpedance amplifier (TIA) and post amplifiers (PA) in 90 nm CMOS (Design 1) whereas in 65 nm CMOS (Design 2) an offset compensation block and a transconductor is incorporated to improve the robustness of the overall receiver front-end.The transimpedance amplifier in both designs is implemented with the shunt feedback topology and the post amplifiers in 90 nm and 65 nm design use the common source topology loaded with modified active inductors and the Cherry-Hooper inverter based topology, respectively. In order to make the receiver front-end power and bandwidth scalable, a current controlling PMOS array and a tuneable resistive bank is implemented in both designs. The Design 1 is able to vary the supported data rate from 1.25 Gb/s to 15 Gb/s. The gain at each data rate is ~ 84 dBΩ. The overall power dissipation varies from 0.94 mW to 7.46 mW as the data rate scales, maintaining an energy per bit lower than 800 fJ at all data rates using a 1.2 V power supply. The input referred noise density varies from 4.31 pA/√Hz to 14.27 pA/√Hz. In the Design 2, the receiver front-end can be tuned from 1.25 Gb/s to 20 Gb/s maintaining a fixed gain of ~75 dBΩ. The power dissipation in this case varies from 0.32 mW to 13.5 mW as the data rate scales up, maintaining energy per bit less than 700 fJ using a 1 V power supply. The input referred noise density varies from 8.46 pA/√Hz to 18 pA/√Hz. Simulation shows that Design 1 is not robust enough against the mismatch and global process variations whereas Design 2 is much more robust against these effects. This type of front-end has applications in links that vary data rate in response to system requirements. Additionally, the lowest data rate can be act as an idle mode which receives data used only to maintain transmitter and receiver synchronization.