Interconnect-aware scheduling and resource allocation for high-level synthesis
A high-level architectural synthesis can be described as the process of transforming a behavioral description into a structural description. The scheduling, processor allocation, and register binding are the most important tasks in the high-level synthesis. In the past, it has been possible to focus...
| Main Author: | |
|---|---|
| Format: | Others |
| Published: |
2009
|
| Online Access: | http://spectrum.library.concordia.ca/976312/1/NR63451.pdf Itradat, Awni <http://spectrum.library.concordia.ca/view/creators/Itradat=3AAwni=3A=3A.html> (2009) Interconnect-aware scheduling and resource allocation for high-level synthesis. PhD thesis, Concordia University. |