A recursive computation of the 2-D DCT : algorithm, architectures and FPGA implementation

• Main Author: An, Shaofeng
• Format: Others
• Published: 2008
• Online Access: http://spectrum.library.concordia.ca/975639/1/MR40877.pdf; An, Shaofeng <http://spectrum.library.concordia.ca/view/creators/An=3AShaofeng=3A=3A.html> (2008) A recursive computation of the 2-D DCT : algorithm, architectures and FPGA implementation. Masters thesis, Concordia University.

The discrete cosine transform (DCT) is widely used in the area of signal and image processing. The 2-D DCT has been used in image compression and become part of image and video standards. The 2-D DCT computation involves a large amount of data. Many applications require the systems to be in small volume and operate in real-time. Designing such a system for 2-D DCT is a challenging task. In this thesis, a new recursive algorithm and two types of circuit architectures are presented for the computation of the 2-D DCT. The new algorithm permits to compute the 2-D DCT by a simple procedure of the 1-D recursive calculations involving only cosine coefficients. A recursive kernel for the proposed algorithm contains a small number of operations. Also, it requires a smaller number of pre-computed data compared to many of existing algorithms in the same category. The kernel can be easily implemented in a simple circuit block with a short critical delay path. In order to evaluate the performance improvement resulting from the new algorithm, an architecture for the 2-D DCT designed by direct mapping from the computation structure of the proposed algorithm has been implemented on an FPGA board. The results show that the reduction of the hardware consumption can easily reach 25% and the clock frequency can increase 17% compared to a system implementing a recently reported 2-D DCT recursive algorithm. For a further reduction of the hardware, another architecture has been proposed for the same 2-D DCT computation. Using one recursive computation block to perform different functions in each clock cycle, this architecture needs only approximately one half of the hardware that is required in the first architecture, which has been confirmed by an FPGA implementation