Architecture and circuit techniques for a 2 GHz advanced high-speed bus SoC interconnect infrastructure
A key issue with high performance SoC platforms is how to interconnect their modules to effectively transfer large amounts of data in real-time. Today's most practical communication infrastructures are bus-based due to the small number of processing elements residing on a silicon die. Since the...
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2005
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| Online Access: | http://spectrum.library.concordia.ca/8313/1/MR04379.pdf Landry, Alexandre <http://spectrum.library.concordia.ca/view/creators/Landry=3AAlexandre=3A=3A.html> (2005) Architecture and circuit techniques for a 2 GHz advanced high-speed bus SoC interconnect infrastructure. Masters thesis, Concordia University. |
Internet
http://spectrum.library.concordia.ca/8313/1/MR04379.pdfLandry, Alexandre <http://spectrum.library.concordia.ca/view/creators/Landry=3AAlexandre=3A=3A.html> (2005) Architecture and circuit techniques for a 2 GHz advanced high-speed bus SoC interconnect infrastructure. Masters thesis, Concordia University.