Syntactic model reduction for hardware verification
Microelectronics systems become more and more complex, making the detection of errors extremely difficult. Model checking, as a formal hardware verification technique, can potentially catch subtle hardware design errors. It is used to automatically verify temporal properties on finite state systems....
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| Format: | Others |
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2003
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| Online Access: | http://spectrum.library.concordia.ca/2074/1/MQ77694.pdf Hussein, Mohamed H. Zaki <http://spectrum.library.concordia.ca/view/creators/Hussein=3AMohamed_H=2E_Zaki=3A=3A.html> (2003) Syntactic model reduction for hardware verification. Masters thesis, Concordia University. |