Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. The concept is rooted in the pro...
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| Language: | en |
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2012
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| Online Access: | http://hdl.handle.net/10012/6644 |