A 'Phase Reset' Scheme for an 8-11Gb/s Bang-Bang CDR in 65nm CMOS
This thesis presents the design and implementation of a CDR with 'phase reset.' By continually 'resetting' the phase of the recovered clock to be aligned with data, cycle-slipping and bit errors during the lock process are reduced. This concept was demonstrated in a full-rate 8-1...
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| Language: | en_ca |
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2013
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| Online Access: | http://hdl.handle.net/1807/65434 |
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