Analytical Modelling of Carrier Depletion Silicon-on-insulator Optical Modulation Diodes

• Main Author: Jayatilleka, Hasitha
• Other Authors: Poon, Joyce
• Language: en_ca
• Published: 2013
• Subjects: Optoelectronics; Modulators; PN junctions; Photonics; 0544
• Online Access: http://hdl.handle.net/1807/42970

We derive an analytical model for the depletion capacitance of silicon-on-insulator (SOI) optical modulation diodes. This model accurately describes the parasitic fringe capacitances due to a lateral pn junction and can be extended to other geometries, such as vertical and interleaved junctions. Analytical results show excellent agreement with numerical simulations. The model is used to identify the waveguide slab to rib height ratio as a key geometric scaling parameter for the modulation e ciency and bandwidth for lateral diodes. We characterise the fringe capacitance as a parasitic e ffect that leads to a decrease of about 20% in modulation bandwidth of typical SOI diodes without a corresponding increase in modulation effi ciency. From the scaling relations, the most e ffective way to increase the modulation bandwidth is to reduce the series resistance of the diode. In the light of our analysis, we propose high-speed and low power microdisk structures for future SOI modulators.