| Summary: | This thesis proposes a automated test case generation technique for the aim of verifying/debugging High-level synthesis (HLS) tools. The work in this thesis builds a framework that automatically generates random programs with user specified features. These programs are used to verify the correctness of the compiled hardware by comparing the hardware simulation results with the software execution results. This way, users can have a large number of benchmarks to test their algorithms for HLS without having to manually develop test programs. The tool also provides additional ways of analyzing performance of HLS tools.
Rather than being a replacement, this technique should serve as a useful complement to existing manually constructed test suites. Together, they can provide more comprehensive verification and analysis for HLS tools.
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