Incremental Power Grid Verification

• Main Author: Abhishek
• Other Authors: Najm, Farid N.
• Language: en_ca
• Published: 2012
• Subjects: EDA; Power Grid Verification; 0544
• Online Access: http://hdl.handle.net/1807/33311

Verification of the on-die power grid is a key step in the design of complex high performance integrated circuits. For the very large grids in modern designs, incremental verification is highly desirable, because it allows one to skip the verification of a certain section of the grid (internal nodes) and instead, verify only the rest of the grid (external nodes). The focus of this work is to develop efficient techniques for incremental verification in the context of vectorless constraints-based grid verification, under dynamic conditions. The traditional difficulty is that the dynamic case requires iterative analysis of both the internal and the external sections. A solution in the transient case is provided through two key contributions: 1) a bound on the internal nodes’ voltages is developed that eliminates the need for iterative analysis, and 2) a multi-port Norton approach is used to construct a reduced macromodel for the internal section.