A Low-power Pipeline ADC with Front-end Capacitor-sharing
This thesis presents the design and experimental results of a low-power pipeline ADC that applies front-end capacitor-sharing. The ADC operates at 20 MS/s, resolves 1.5 bits/stage, and is implemented in IBM 0.13um technology. The purpose of the technique is to reduce power consumption in the front-e...
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| Language: | en_ca |
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2012
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| Online Access: | http://hdl.handle.net/1807/32294 |