A Spin-torque Transfer MRAM in 90nm CMOS

A Spin-torque Transfer MRAM in 90nm CMOS

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This thesis presents the design and implementation of a high-speed read-access STT MRAM. The proposed design includes a 2T1MTJ cell topology, along with two different read schemes: current-based and voltage-based. Compared to the conventional read scheme with 1T1MTJ cells, the proposed design is cap...

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Bibliographic Details
Main Author: Song, Hui William
Other Authors: Sheikholeslami, Ali
Language:en_ca
Published: 2011
Subjects:
Spintronics
Solid-state memory
Non-volatile
MRAM
STT
MTJ
High-speed read-access
2T1MTJ cell
0544
Online Access:http://hdl.handle.net/1807/29628
id ndltd-LACETR-oai-collectionscanada.gc.ca-OTU.1807-29628
record_format oai_dc
spelling ndltd-LACETR-oai-collectionscanada.gc.ca-OTU.1807-296282013-04-20T05:22:06ZA Spin-torque Transfer MRAM in 90nm CMOSSong, Hui WilliamSpintronicsSolid-state memoryNon-volatileMRAMSTTMTJHigh-speed read-access2T1MTJ cell0544This thesis presents the design and implementation of a high-speed read-access STT MRAM. The proposed design includes a 2T1MTJ cell topology, along with two different read schemes: current-based and voltage-based. Compared to the conventional read scheme with 1T1MTJ cells, the proposed design is capable of reducing the loading on the read circuit to minimize the read access time. A complete STT MRAM test chip including the proposed and the conventional schemes was fabricated in 90nm CMOS technology. The 16kb test chip's measurement results confirm a read access time of 6ns and a write access time of 10ns. The read time is 25% faster than other works of similar array size published thus far, while the write time is able to match the fastest result.Sheikholeslami, Ali2011-062011-08-25T19:38:04ZNO_RESTRICTION2011-08-25T19:38:04Z2011-08-25Thesishttp://hdl.handle.net/1807/29628en_ca
collection NDLTD
language en_ca
sources NDLTD
topic Spintronics
Solid-state memory
Non-volatile
MRAM
STT
MTJ
High-speed read-access
2T1MTJ cell
0544
spellingShingle Spintronics
Solid-state memory
Non-volatile
MRAM
STT
MTJ
High-speed read-access
2T1MTJ cell
0544
Song, Hui William
A Spin-torque Transfer MRAM in 90nm CMOS
description This thesis presents the design and implementation of a high-speed read-access STT MRAM. The proposed design includes a 2T1MTJ cell topology, along with two different read schemes: current-based and voltage-based. Compared to the conventional read scheme with 1T1MTJ cells, the proposed design is capable of reducing the loading on the read circuit to minimize the read access time. A complete STT MRAM test chip including the proposed and the conventional schemes was fabricated in 90nm CMOS technology. The 16kb test chip's measurement results confirm a read access time of 6ns and a write access time of 10ns. The read time is 25% faster than other works of similar array size published thus far, while the write time is able to match the fastest result.
author2 Sheikholeslami, Ali
author_facet Sheikholeslami, Ali
Song, Hui William
author Song, Hui William
author_sort Song, Hui William
title A Spin-torque Transfer MRAM in 90nm CMOS
title_short A Spin-torque Transfer MRAM in 90nm CMOS
title_full A Spin-torque Transfer MRAM in 90nm CMOS
title_fullStr A Spin-torque Transfer MRAM in 90nm CMOS
title_full_unstemmed A Spin-torque Transfer MRAM in 90nm CMOS
title_sort spin-torque transfer mram in 90nm cmos
publishDate 2011
url http://hdl.handle.net/1807/29628
work_keys_str_mv AT songhuiwilliam aspintorquetransfermramin90nmcmos
AT songhuiwilliam spintorquetransfermramin90nmcmos
_version_ 1716583555635609600

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