| Summary: | As modern integrated circuit design pushes further into the deep submicron era, the pseudo-random design structures become more and more difficult to fabricate and result in a yield reduction. To deal with process limitations due to photolithographic resolution, standard cell ASICs (SC-ASIC) may eventually need to be replaced by a more structured form of logic, such as programmable logic array (PLA). However, in order to compete with SC-ASIC, the PLA needs to be improved on delay, power and energy consumption.
Here, we will explore a novel PLA structure by combining one design having the best delay performance with a “product line merging process” to minimize power. We have simulated the different approaches on two sets of benchmark circuits using HSpice. As a result, the combination of the two methods produces the highest energy reduction among all prior PLA designs.
Next, algorithms are introduced for partitioning multi-output PLAs into smaller size sub-PLAs to further reduce delay and area. Finally, the performance of the improved PLA is compared with SC-ASIC. We found that the new PLA is faster or at least has the same speed as SC-ASIC implementation. However, the energy consumption is still more than twice as much as SC-ASIC design.
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