FPGA emulation for critical-path coverage analysis
A major task in post-silicon validation is timing validation: it can be incredibly difficult to ensure a new chip meets timing goals. Post-silicon validation is the first opportunity to check timing with real silicon under actual operating conditions and workloads. However, post-silicon tests suffer...
Main Author: | Balston, Kyle |
---|---|
Language: | English |
Published: |
University of British Columbia
2012
|
Online Access: | http://hdl.handle.net/2429/43426 |
Similar Items
-
FPGA emulation for critical-path coverage analysis
by: Balston, Kyle
Published: (2012) -
FPGA emulation for critical-path coverage analysis
by: Balston, Kyle
Published: (2012) -
Performance Driven Logic Replication for FPGA Emulation System
by: Chen, Chih Heng, et al.
Published: (2016) -
FPGA Implementation of a UWB Channel Model Emulator
by: Pu-Hung Lin, et al.
Published: (2009) -
Design and Emulation of All-Digital Phase-Locked Loop on FPGA
by: Saichandrateja Radhapuram, et al.
Published: (2019-11-01)