| Summary: | System-on-chip (SoC) with reuse of intellectual property (IP) is gaining acceptance as the preferred
style for integrated circuit (IC) designs. Increasing demand for analog/mixed-signal (AMS) cores on
SoCs is creating a need for new design methodologies and tools that facilitate the creation and
integration of reusable AMS IP. In this work, a practical definition of AMS IP and an associated
design-for-reuse process is proposed.
This thesis begins by investigating the issues of reusable AMS IP using a phase-locked loop (PLL)
as the design vehicle. In the first pass, a PLL is designed without reusable IP. In the process of
designing this PLL, the issues of how the IP should be defined for improved reusability and ease of
design is addressed. Then a suitable design methodology is proposed to use the IP in a design flow.
Firm IP is suggested as the most appropriate format to deliver the AMS IP library components.
Unlike hard IP, this form allows ease of migration of IP from foundry-to-foundry, customer-tocustomer
and application-to-application. Then, a design methodology is developed for constraintdriven
top-down design and model-driven bottom-up characterization of the cores. Once the
design topology is selected, an IP hardening flow is described to produce a physical layout.
To validate the approach, the primary specifications of the first PLL were then changed and a
second architecture was generated using the proposed design methodology. The time needed to
design the second PLL is shown to be greatly reduced (by a factor of four) for comparable
performance.
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